US5294561A
Expired / Lapsed
US
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Method for manufacturing highly-integrated stacked capacitor
Assignee: NEC Corp
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Filing: 1993-08-25
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Granted: 1994-03-15
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Expires: 2013-08-25
Abstract
Abstract An impurity doped region is formed in a semiconductor substrate, and an insulating layer is formed thereon. A conductive layer is formed and is patterned by a photolithography process Then, a conductive sidewall is formed inside of the conductive layer. The insulating layer is etched with a mask of the conductive sidewall and the conductive layer to create a contact hole leading to the impurity doped region. A capacitor lower electrode layer is deposited within the contact hole. Thus, a capacitor insulating layer and a capacitor upper electrode layer are formed, to obtain a stacked capacitor.
Inventors
- 👤 Takaho Tanigawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 12:59
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10B12/30; H10B12/48; H10B12/482; H10D; H10D1/00; H10D1/60; H10D1/68; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/081
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
159 words
A method for manufacturing a stacked capacitor, comprising the steps of: forming an impurity doped region within a semiconductor substrate, the conductivity type of said impurity doped region being opposite to that of said semiconductor substrate; forming an insulating layer on said semiconductor substrate; forming a conductive layer on said insulating layer; patterning said conductive layer to create an opening therein, said opening being located over said impurity doped region; forming a conductive sidewall along the inside of the opening of said conductive layer; patterning said insulating layer with a mask of said conductive layer and said conductive sidewall to create a contact hole leading to said impurity doped region; forming a capacitor lower electrode layer, said conductive lower electrode layer being electrically connected to said impurity doped region, said conductive layer and said conductive sidewall; forming a capacitor insulating layer on said capacitor lower electrode layer; and forming a capacitor upper electrode layer on said capacitor insulating layer.
Claim 2
Independent Claim
159 words
A method for manufacturing a stacked capacitor, comprising the steps of: forming an impurity doped region within a semiconductor substrate, the conductivity type of said impurity doped region being opposite to that of said semiconductor substrate; forming an insulating layer on said semiconductor substrate; forming a conductive layer on said insulating layer; patterning said conductive layer to create an opening therein, said opening being located over said impurity doped region; forming a conductive sidewall along the inside of the opening of said conductive layer; patterning said insulating layer with a mask of said conductive layer and said conductive sidewall to create a contact hole leading to said impurity doped region; forming a capacitor lower electrode layer, said conductive lower electrode layer being electrically connected to said impurity doped region, said conductive layer and said conductive sidewall; forming a capacitor insulating layer on said capacitor lower electrode layer; and forming a capacitor upper electrode layer on said capacitor insulating layer.
Claim 3
Dependent Claim
18 words
A method as set forth in claim 1, wherein an upper surface of said insulating layer is flat.
Claim 4
Independent Claim
279 words
A method for manufacturing a semiconductor memory device comprising the steps of: forming a thick insulating layer on a semiconductor substrate of a first conductivity type; forming a gate insulating layer on said semiconductor substrate; forming a gate electrode layer on said gate insulating layer; forming a source region and a drain region by introducing impurities of a second conductivity type opposite to said first conductivity type into said semiconductor substrate with a mask of said thick insulating layer and said gate electrode layer; forming a first insulating layer on said semiconductor substrate, said thick insulating layer and said gate electrode layer; forming a conductive layer on said first insulating layer; patterning said conductive layer to create an opening therein said opening being located over said drain region; forming a conductive sidewall along the inside of the opening of said conductive layer; patterning said first insulating layer with a mask of said conductive layer and said conductive sidewall to create a contact hole leading to said drain region; forming a capacitor lower electrode layer, said conductive lower electrode layer being electrically connected to said drain region, said conductive layer and said conductive sidewall; forming a capacitor insulating layer said capacitor lower electrode layer; forming a capacitor upper electrode layer on said capacitor insulating layer; patterning said capacitor upper electrode layer, said capacitor insulating layer and said capacitor lower electrode layer; forming a second insulating layer on said capacitor upper electrode and said first insulating layer; patterning said second insulating layer and said first insulating layer to create a contact hole leading to said source region; and forming a bit line electrode layer to be connected to said source region.
Claim 5
Independent Claim
279 words
A method for manufacturing a semiconductor memory device comprising the steps of: forming a thick insulating layer on a semiconductor substrate of a first conductivity type; forming a gate insulating layer on said semiconductor substrate; forming a gate electrode layer on said gate insulating layer; forming a source region and a drain region by introducing impurities of a second conductivity type opposite to said first conductivity type into said semiconductor substrate with a mask of said thick insulating layer and said gate electrode layer; forming a first insulating layer on said semiconductor substrate, said thick insulating layer and said gate electrode layer; forming a conductive layer on said first insulating layer; patterning said conductive layer to create an opening therein said opening being located over said drain region; forming a conductive sidewall along the inside of the opening of said conductive layer; patterning said first insulating layer with a mask of said conductive layer and said conductive sidewall to create a contact hole leading to said drain region; forming a capacitor lower electrode layer, said conductive lower electrode layer being electrically connected to said drain region, said conductive layer and said conductive sidewall; forming a capacitor insulating layer said capacitor lower electrode layer; forming a capacitor upper electrode layer on said capacitor insulating layer; patterning said capacitor upper electrode layer, said capacitor insulating layer and said capacitor lower electrode layer; forming a second insulating layer on said capacitor upper electrode and said first insulating layer; patterning said second insulating layer and said first insulating layer to create a contact hole leading to said source region; and forming a bit line electrode layer to be connected to said source region.
Claim 6
Dependent Claim
18 words
A method as set forth in claim 3, wherein an upper surface said first insulating layer is flat.
Claim 7
Independent Claim
261 words
A method for manufacturing a semiconductor memory device comprising the steps of: forming a thick insulating layer on a semiconductor substrate of a first conductivity type; forming a gate insulating layer on said semiconductor substrate; forming a gate electrode layer on said gate insulating layer; forming a source region and a drain region by introducing impurities of a second conductivity type opposite to said first conductivity type into said semiconductor substrate with a mask of said thick insulating layer and said gate electrode layer; forming an first insulating layer on said semiconductor substrate, said thick insulating layer and said gate electrode layer; patterning said first insulating layer to create a contact hole leading to said source region; forming a bit line electrode layer to be connected to said source region; forming a second insulating layer on said bit line electrode layer and said first insulating layer; forming a conductive layer on said second insulating layer; patterning said conductive layer to create an opening therein, said opening being located over said drain region; forming a conductive sidewall along the inside of the opening of said conductive layer; patterning said first and second insulating layers with a mask of said conductive layer and said conductive sidewall to create a contact hole leading to said drain region; forming a capacitor lower electrode layer, said conductive lower electrode layer being electrically connected to said drain region, said conductive layer and said conductive sidewall; forming a capacitor insulating layer on said capacitor lower electrade layer; forming a capacitor upper electrode layer on said capacitor insulating layer.
Claim 8
Independent Claim
261 words
A method for manufacturing a semiconductor memory device comprising the steps of: forming a thick insulating layer on a semiconductor substrate of a first conductivity type; forming a gate insulating layer on said semiconductor substrate; forming a gate electrode layer on said gate insulating layer; forming a source region and a drain region by introducing impurities of a second conductivity type opposite to said first conductivity type into said semiconductor substrate with a mask of said thick insulating layer and said gate electrode layer; forming an first insulating layer on said semiconductor substrate, said thick insulating layer and said gate electrode layer; patterning said first insulating layer to create a contact hole leading to said source region; forming a bit line electrode layer to be connected to said source region; forming a second insulating layer on said bit line electrode layer and said first insulating layer; forming a conductive layer on said second insulating layer; patterning said conductive layer to create an opening therein, said opening being located over said drain region; forming a conductive sidewall along the inside of the opening of said conductive layer; patterning said first and second insulating layers with a mask of said conductive layer and said conductive sidewall to create a contact hole leading to said drain region; forming a capacitor lower electrode layer, said conductive lower electrode layer being electrically connected to said drain region, said conductive layer and said conductive sidewall; forming a capacitor insulating layer on said capacitor lower electrade layer; forming a capacitor upper electrode layer on said capacitor insulating layer.
Claim 9
Dependent Claim
18 words
A method as set forth in claim 5, wherein an upper surface said first insulating layer is flat.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1997-03-14 | 1997-09-13 | 1998-03-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-03-14 | 2001-09-13 | 2002-03-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-03-14 | 2005-09-13 | 2006-03-15 | $7700.00 | Window Closed / Lapsed |