US5293500A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Parallel processing method and apparatus
Assignee: Mitsubishi Electric Corp
•
Filing: 1993-05-27
•
Granted: 1994-03-08
•
Expires: 2013-05-27
Abstract
Abstract A parallel processor is provided with a plurality of independently operable command units and a plurality of function units each connected to the command unit. A data unit, a register file, and a carry bit are shared such that the command and function units operate in parallel without any conflict. A priority scoreboard is provided to control the register file so that the command units operate independently according to the parallelism of a program, and detect and avoid a contention for a register according to the order of priority, making simultaneous execution of a plurality of commands possible, resulting in the increased process speed.
Inventors
- 👤 Hitoshi Ishida
- 👤 Shigeyuki Kazama
- 👤 Minoru Shiga
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 23:45
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3836; G06F9/3838; G06F9/3885
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
170 words
A parallel processor for an information processing system having a plurality of processing units for performing general computer operations such as fetching, decoding, executing and storing commands, which comprises: a plurality of register files provided for each of said processing units and each consisting of a plurality of registers for storing predetermined information; an execution order arbiter for detecting a register contention between said processing units when a plurality of said processing units access the same register file, and adjusting an execution order for said processing units according to a predetermined priority order that a preceding command is executed before a succeeding command; and a selector for enabling independent read operations by each of said processing units from the registers of each of said register files and simultaneous write operations by each of said processing units onto the registers of all of said register files, and controlled by said execution order arbiter to enable one of said execution order when a plurality of said processing units access the register simultaneously.
Claim 2
Dependent Claim
170 words
A parallel processor for an information processing system having a plurality of processing units for performing general computer operations such as fetching, decoding, executing and storing commands, which comprises: a plurality of register files provided for each of said processing units and each consisting of a plurality of registers for storing predetermined information; an execution order arbiter for detecting a register contention between said processing units when a plurality of said processing units access the same register file, and adjusting an execution order for said processing units according to a predetermined priority order that a preceding command is executed before a succeeding command; and a selector for enabling independent read operations by each of said processing units from the registers of each of said register files and simultaneous write operations by each of said processing units onto the registers of all of said register files, and controlled by said execution order arbiter to enable one of said execution order when a plurality of said processing units access the register simultaneously.
Claim 3
Dependent Claim
26 words
The parallel operating data processor of claim 1, wherein said predetermined priority order is such that a higher execution priority is given to a preceding command.
Claim 4
Dependent Claim
206 words
A parallel processor for an information processing system having a plurality of command units for performing general computer operations such as fetching, decoding, and transferring commands and a plurality of processing units for processing data, said parallel processor comprising: a register file shared by a plurality of said processing units for storing predetermined information; register contention avoiding means for detecting a register contention between said processing units which occurs when said processing units access said register file and for avoiding said register contention according to a predetermined priority order that a preceding command is executed before a succeeding command; data units provided for each of said processing units for executing data read/write operations between said memory and said register file; and a controller for detecting a memory address contention which occurs when said data units access said memory and determining an execution order for the access of said data units according to said predetermined priority order so that each of said command units and each of said data units process data in parallel according to said predetermined priority order when said command units issue a plurality of accesses to said register file simultaneously and when said data units issue a plurality of accesses to said memory.
Claim 5
Dependent Claim
206 words
A parallel processor for an information processing system having a plurality of command units for performing general computer operations such as fetching, decoding, and transferring commands and a plurality of processing units for processing data, said parallel processor comprising: a register file shared by a plurality of said processing units for storing predetermined information; register contention avoiding means for detecting a register contention between said processing units which occurs when said processing units access said register file and for avoiding said register contention according to a predetermined priority order that a preceding command is executed before a succeeding command; data units provided for each of said processing units for executing data read/write operations between said memory and said register file; and a controller for detecting a memory address contention which occurs when said data units access said memory and determining an execution order for the access of said data units according to said predetermined priority order so that each of said command units and each of said data units process data in parallel according to said predetermined priority order when said command units issue a plurality of accesses to said register file simultaneously and when said data units issue a plurality of accesses to said memory.
Claim 6
Dependent Claim
44 words
The parallel operating data processor of claim 3, wherein said predetermined priority order is set as follows: 0- Command under execution in the preceding stage 1- Command pending 2- Command accepted by a first data unit 3- Command accepted by a second data unit.
References Cited (Backward Citations)
US3629853A
Cited
US4088462A
Cited
US4626989A
Cited
US4594655A
Cited
US4903196A
Cited
US4811208A
Cited
US4766566A
Cited
US4891753A
Cited
US5075840A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-03-07 | 1997-09-06 | 1998-03-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-03-07 | 2001-09-06 | 2002-03-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-03-07 | 2005-09-06 | 2006-03-08 | $7700.00 | Window Closed / Lapsed |