Patent US5293496A successfully refreshed from Google Patents.
US5293496A
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Inhibit write apparatus and method for preventing bus lockout
Assignee: Unisys Corp
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Filing: 1993-01-12
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Granted: 1994-03-08
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Expires: 2013-01-12
Abstract
Abstract A User bus lockout prevention mechanism for use in a time-shared busy multiple bus User, computer architecture where bus Users include private cache systems which perform a cache cycle when a WRITE TO MEMORY instruction occurs on the bus to determine if data cached from main memory has been overwritten in main memory. A User can be locked out from use of the bus if a synchronism occurs between repetative cache cycles and periodicity of the Retry mechanism of the User. Bus lockout is prevented by the User with the cache issuing an INHIBIT WRITE to the bus when a cache cycle is being performed. Other Users inhibit issuing WRITE TO MEMORY requests to the bus until the INHIBIT WRITE signal terminates. Bus requests other than a write request may be issued to the bus during INHIBIT WRITE.
Inventors
- 👤 Theodore C. White
- 👤 Jayesh V. Sheth
- 👤 Dan T. Tran
- 👤 Paul B. Ricci
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 04:06
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/36; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0815; G06F12/0831
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
222 words
In a computer system having a time-shared bus with a plurality of bus Users and a main memory coupled to said bus, said plurality of bus Users including first and second bus Users, said first bus User operative to issue bus requests to said bus to use said bus and to receive bus grants, granting bus use thereto, said bus requests including a write request to place a WRITE instruction on said bus to write to said main memory at an address specified by said WRITE instructions, said second bus User having a cache memory system for storing words from said main memory, said cache memory system having cache cycle control means for effecting a cache cycle in response to said WRITE instruction, said cache cycle being operative to determine if said cache memory system is storing a word from said main memory from said address specified by said WRITE instruction and to invalidate said word in said cache memory system; bus lockout prevention apparatus comprising inhibit write means in said second bus User for issuing an INHIBIT WRITE signal to said bus during said cache cycle, and inhibiting means in said first bus User for inhibiting said write request in response to said INHIBIT WRITE signal and for issuing said write request to said bus when said INHIBIT WRITE signal terminates.
Claim 2
Dependent Claim
222 words
In a computer system having a time-shared bus with a plurality of bus Users and a main memory coupled to said bus, said plurality of bus Users including first and second bus Users, said first bus User operative to issue bus requests to said bus to use said bus and to receive bus grants, granting bus use thereto, said bus requests including a write request to place a WRITE instruction on said bus to write to said main memory at an address specified by said WRITE instructions, said second bus User having a cache memory system for storing words from said main memory, said cache memory system having cache cycle control means for effecting a cache cycle in response to said WRITE instruction, said cache cycle being operative to determine if said cache memory system is storing a word from said main memory from said address specified by said WRITE instruction and to invalidate said word in said cache memory system; bus lockout prevention apparatus comprising inhibit write means in said second bus User for issuing an INHIBIT WRITE signal to said bus during said cache cycle, and inhibiting means in said first bus User for inhibiting said write request in response to said INHIBIT WRITE signal and for issuing said write request to said bus when said INHIBIT WRITE signal terminates.
Claim 3
Dependent Claim
43 words
The apparatus of claim 1 wherein said inhibiting means is operative to inhibit only said write request in response to said INHIBIT WRITE signal and not to inhibit said bus requests other than said write request in response to said INHIBIT WRITE signal.
Claim 4
Dependent Claim
102 words
The apparatus of claim 1 wherein said inhibit write means comprises detecting means coupled to said bus for detecting said WRITE instruction, thereby providing a detected WRITE instructions, and sequencing means responsive to said detected WRITE instruction for signalling said cache cycle control means to initiate said cache cycle and for simultaneously issuing said INHIBIT WRITE signal to said bus, said cache cycle control means being operative to issue a CACHE CYCLE COMPLETE signal to said sequencing means when said cache cycle completes, said sequencing means being operative in response to said CACHE CYCLE COMPLETE signal to terminate said INHIBIT WRITE signal.
Claim 5
Dependent Claim
13 words
The apparatus of claim 3 wherein said sequencing means comprises a state machine.
Claim 6
Dependent Claim
98 words
The apparatus of claim 1 wherein said first bus User is operative to generate a REQUEST signal to use said bus and a WRITE signal when a bus request is said write request, and said inhibiting means comprises logic gate means responsive to said REQUEST signal, said WRITE signal and said INHIBIT WRITE signal for inhibiting said REQUEST signal from said bus in the presence of said WRITE signal and said INHIBIT WRITE signal and for issuing said REQUEST signal to said bus in the presence of said WRITE signal and the absence of said INHIBIT WRITE signal.
Claim 7
Dependent Claim
34 words
The apparatus of claim 1 further including arbiter means coupled to said bus for assigning bus request priority to said plurality of bus Users in a manner tending to grant equal bus access thereto.
Claim 8
Dependent Claim
215 words
In a computer system having a time-shared bus with a plurality of bus Users and a main memory coupled to said busy said plurality of bus Users including first and second bus Users, said first bus User operative to issue bus requests to said bus to use said bus and to receive bus grants, granting bus use thereto, said bus requests including a write request to place a WRITE instruction on said bus to write to said main memory at an address specified by said WRITE instruction, said second bus User having a cache memory system for storing words from said main memory, said cache memory system having cache cycle control means for effecting a cache cycle in response to said WRITE instruction, said cache cycle being operative to determine if said cache memory system is storing a word from said main memory from said address specified by said WRITE instruction and to invalidate said word in said cache memory system; a bus lockout prevention method comprising issuing an INHIBIT WRITE signal by said second bus User to said bus during said cache cycle, and inhibiting said write request in said first bus User in response to said INHIBIT WRITE signal and issuing said write request to said bus when said INHIBIT WRITE signal terminates.
Claim 9
Dependent Claim
215 words
In a computer system having a time-shared bus with a plurality of bus Users and a main memory coupled to said busy said plurality of bus Users including first and second bus Users, said first bus User operative to issue bus requests to said bus to use said bus and to receive bus grants, granting bus use thereto, said bus requests including a write request to place a WRITE instruction on said bus to write to said main memory at an address specified by said WRITE instruction, said second bus User having a cache memory system for storing words from said main memory, said cache memory system having cache cycle control means for effecting a cache cycle in response to said WRITE instruction, said cache cycle being operative to determine if said cache memory system is storing a word from said main memory from said address specified by said WRITE instruction and to invalidate said word in said cache memory system; a bus lockout prevention method comprising issuing an INHIBIT WRITE signal by said second bus User to said bus during said cache cycle, and inhibiting said write request in said first bus User in response to said INHIBIT WRITE signal and issuing said write request to said bus when said INHIBIT WRITE signal terminates.
Claim 10
Dependent Claim
40 words
The method of claim 7 wherein said inhibiting step comprises inhibiting only said write request in response to said INHIBIT WRITE signal and not inhibiting said bus requests other than said write request in response to said INHIBIT WRITE signal.
Claim 11
Dependent Claim
53 words
The method of claim 7 wherein said issuing step comprises detecting said WRITE instruction, activating said cache cycle control means to initiate said cache cycle in response to detecting said WRITE instruction and simultaneously issuing said INHIBIT WRITE signal to said bus, and terminating said INHIBIT WRITE signal when said cache cycle completes.
Claim 12
Dependent Claim
27 words
The method of claim 7 further including arbitrating bus request priority to said plurality of bus Users in a manner tending to grant equal bus access thereto.
Claim 13
Dependent Claim
227 words
In a computer system having a time-shared bus with a plurality of bus Users and a main memory coupled to said bus, said plurality of bus Users including first and second and bus Users, said first bus user operative to issue bus requests to said bus to use said bus and to receive bus grants, granting bus use thereto, said bus requests including a write request to place a WRITE instruction on said bus to write to said main memory at an address specified by said WRITE instruction, said second bus User having a cache memory system for storing words from said main memory, said cache memory system having cache cycle control means for effecting a cache cycle in response to said WRITE instruction, said cache cycle being operative to determine if said cache memory system is storing a word from said main memory from said address specified by said WRITE instruction and to invalidate said word in said cache memory system; bus lockout prevention apparatus comprising inhibit write means in said second bus User for issuing an INHIBIT WRITE signal to said bus during said cache cycle, and inhibiting means in said first bus User for inhibiting placing said WRITE instruction on said bus in response to said INHIBIT WRITE signal and for placing said WRITE instruction on said bus when said INHIBIT WRITE signal terminates.
Claim 14
Dependent Claim
227 words
In a computer system having a time-shared bus with a plurality of bus Users and a main memory coupled to said bus, said plurality of bus Users including first and second and bus Users, said first bus user operative to issue bus requests to said bus to use said bus and to receive bus grants, granting bus use thereto, said bus requests including a write request to place a WRITE instruction on said bus to write to said main memory at an address specified by said WRITE instruction, said second bus User having a cache memory system for storing words from said main memory, said cache memory system having cache cycle control means for effecting a cache cycle in response to said WRITE instruction, said cache cycle being operative to determine if said cache memory system is storing a word from said main memory from said address specified by said WRITE instruction and to invalidate said word in said cache memory system; bus lockout prevention apparatus comprising inhibit write means in said second bus User for issuing an INHIBIT WRITE signal to said bus during said cache cycle, and inhibiting means in said first bus User for inhibiting placing said WRITE instruction on said bus in response to said INHIBIT WRITE signal and for placing said WRITE instruction on said bus when said INHIBIT WRITE signal terminates.
Claim 15
Dependent Claim
34 words
The apparatus of claim 11 further including arbiter means coupled to said bus for assigning bus request priority to said plurality of bus Users in a manner tending to grant equal bus access thereto.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-03-07 | 1997-09-06 | 1998-03-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-03-07 | 2001-09-06 | 2002-03-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-03-07 | 2005-09-06 | 2006-03-08 | $7700.00 | Window Closed / Lapsed |