Simplified serial selection circuit for serial access in semiconductor memory and operating method thereof

Claim 2

A serial selection circuit for a semiconductor memory comprising: a plurality of selecting lines each connected to a memory cell for selecting a memory cell to be accessed; a plurality of state holding means for respectively holding the state of each of said plurality of selecting lines; activation means responsive to an externally applied clock signal for sequentially activating said plurality of state holding means; and deactivation means responsive to the activation of the state holding means in the subsequent stage for deactivating the state holding means in the preceding stage.

Claim 3

The serial selection circuit for a semiconductor memory according to claim 1, wherein said sequential activation means comprises: means responsive to said externally applied clock signal for generating an activation potential for activating said plurality of state holding means; and activation potential applying means responsive to the activation of the state holding means in the preceding stage for applying the activation potential to the state holding means in the subsequent stage.

Claim 4

The serial selection circuit for a semiconductor memory according to claim 1, wherein said deactivation means comprises: delay means for delaying said externally applied clock signal; means responsive to the clock signal delayed by said delay means for generating a deactivation potential for deactivating said plurality of state holding means; and deactivation potential applying means responsive to the activation of the state holding means in the subsequent stage for applying the deactivation potential to the state holding means in the preceding stage.

Claim 5

The serial selection circuit for a semiconductor memory according to claim 1, wherein each of said state holding means is connected to each of said selecting lines, and comprises flipflop means for holding the potential of the selecting line.

Claim 6

The serial selection circuit for a semiconductor memory according to claim 4, wherein said flipflop means comprises 2 cross-coupled inverter means connected to each of said selecting lines.

Claim 7

The serial selection circuit for a semiconductor memory according to claim 1, wherein said plurality of selecting lines comprise a plurality of word lines each connected to a memory cell.

Claim 8

A serial selection circuit for a semiconductor memory comprising: a plurality of selecting lines each connected to a memory cell for selecting a memory cell to be accessed; a plurality of state holding means for respectively holding the state of each of said plurality of selecting lines; activation means responsive to an externally applied clock signal for sequentially activating said plurality of state holding means; and deactivation means responsive to the activation of the state holding means in the subsequent stage for deactivating the state holding means in the preceding stage; wherein said sequential activation means comprises: means responsive to said externally applied clock signal for generating a first activation signal for activating an odd-numbered one of said plurality of state holding means; means responsive to said externally applied clock signal for generating a second activation signal for activating an even-numbered one of said plurality of state holding means, said first and second activation signals being generated at timings different from each other; means responsive to the activation of the state holding means in the preceding state, and in even-numbered order for applying the first activation signal to the state holding means in the following odd-numbered order, said state holding means in the following odd-numbered order being activated in response to the applied first activation signal; and means responsive to the activation of the state holding means in the preceding state and in odd-numbered order for applying the second activation signal to the state holding means in the following even-numbered order, said state holding means in the following even-numbered order being activated in response to the applied second activation signal.

Claim 9

A serial selection circuit for a semiconductor memory comprising: a plurality of selecting lines each connected to a memory cell for selecting a memory cell to be accessed; a plurality of state holding means for respectively holding the state of each of said plurality of selecting lines; activation means responsive to an externally applied clock signal for sequentially activating said plurality of state holding means; and deactivation means responsive to the activation of the state holding means in the subsequent stage for deactivating the state holding means in the preceding stage; wherein said sequential activation means comprises: means responsive to said externally applied clock signal for generating a first activation signal for activating an odd-numbered one of said plurality of state holding means; means responsive to said externally applied clock signal for generating a second activation signal for activating an even-numbered one of said plurality of state holding means, said first and second activation signals being generated at timings different from each other; means responsive to the activation of the state holding means in the preceding state, and in even-numbered order for applying the first activation signal to the state holding means in the following odd-numbered order, said state holding means in the following odd-numbered order being activated in response to the applied first activation signal; and means responsive to the activation of the state holding means in the preceding state and in odd-numbered order for applying the second activation signal to the state holding means in the following even-numbered order, said state holding means in the following even-numbered order being activated in response to the applied second activation signal.

Claim 10

A serial selection circuit for a semiconductor memory comprising: a plurality of selecting lines each connected to a memory cell for selecting a memory cell to be accessed; a plurality of state holding means for respectively holding the state of each of said plurality of selecting lines; activation means responsive to an externally applied clock signal for sequentially activating said plurality of state holding means; and deactivation means responsive to the activation of the state holding means in the subsequent stage for deactivating the state holding means in the preceding stage; wherein said deactivation means comprises: means responsive to said externally applied clock signal for generating a first deactivation signal for deactivating the one in odd-numbered order of said plurality of state holding means; means responsive to said externally applied clock signal for generating a second deactivation signal for deactivating the one in even-numbered order of said plurality of state holding means, said first and second deactivation signals being generated at timings different from each other; means responsive to the activation of the state holding means in the subsequent stage and in even-numbered order for applying the first deactivation signal to the state holding means in the preceding odd-numbered order, said state holding means in the preceding odd-numbered order being deactivated in response to the applied first deactivation signal; and means responsive to the activation of the state holding means in the subsequent stage and in odd-numbered order for applying the second deactivation signal to the state holding means in the preceding even-numbered order, said state holding means in the preceding even-numbered order being deactivated in response to the applied second deactivation signal.

Claim 11

A serial selection circuit for a semiconductor memory comprising: a plurality of selecting lines each connected to a memory cell for selecting a memory cell to be accessed; a plurality of state holding means for respectively holding the state of each of said plurality of selecting lines; activation means responsive to an externally applied clock signal for sequentially activating said plurality of state holding means; and deactivation means responsive to the activation of the state holding means in the subsequent stage for deactivating the state holding means in the preceding stage; wherein said deactivation means comprises: means responsive to said externally applied clock signal for generating a first deactivation signal for deactivating the one in odd-numbered order of said plurality of state holding means; means responsive to said externally applied clock signal for generating a second deactivation signal for deactivating the one in even-numbered order of said plurality of state holding means, said first and second deactivation signals being generated at timings different from each other; means responsive to the activation of the state holding means in the subsequent stage and in even-numbered order for applying the first deactivation signal to the state holding means in the preceding odd-numbered order, said state holding means in the preceding odd-numbered order being deactivated in response to the applied first deactivation signal; and means responsive to the activation of the state holding means in the subsequent stage and in odd-numbered order for applying the second deactivation signal to the state holding means in the preceding even-numbered order, said state holding means in the preceding even-numbered order being deactivated in response to the applied second deactivation signal.

Claim 12

A serial selection circuit for a semiconductor memory device comprising: first and second selecting lines each connected to a memory cell for selecting a memory cell to be accessed; first and second state holding means for respectively holding the state of each of said first and second selecting lines; sequential activation means responsive to an externally applied clock signal for sequentially activating said first and second state holding means; and deactivation means responsive to the activation of the second state holding means for deactivating the first state holding means.

Claim 13

A serial selection circuit for a semiconductor memory device comprising: first and second selecting lines each connected to a memory cell for selecting a memory cell to be accessed; first and second state holding means for respectively holding the state of each of said first and second selecting lines; sequential activation means responsive to an externally applied clock signal for sequentially activating said first and second state holding means; and deactivation means responsive to the activation of the second state holding means for deactivating the first state holding means.

Claim 14

A sequential selection circuit for sequentially selecting a plurality of signal lines comprising: a plurality of state holding means each connected to each of said plurality of signal lines for holding the state of respective signal line; sequential activation means responsive to an externally applied clock signal for sequentially activating said plurality of state holding means; and deactivation means responsive to the activation of the state holding means in the subsequent stage for deactivating the state holding means subsequent thereto.

Claim 15

A sequential selection circuit for sequentially selecting a plurality of signal lines comprising: a plurality of state holding means each connected to each of said plurality of signal lines for holding the state of respective signal line; sequential activation means responsive to an externally applied clock signal for sequentially activating said plurality of state holding means; and deactivation means responsive to the activation of the state holding means in the subsequent stage for deactivating the state holding means subsequent thereto.

Claim 16

An operating method for a serial selection circuit in a semiconductor memory device, said serial selection circuit comprising: a plurality of selecting lines each connected to a memory cell for selecting a memory cell to be accessed; and a plurality of state holding means for respectively holding the state of each of said plurality of selecting lines, said method comprising the steps of: sequentially activating said plurality of state holding means in response to an externally applied clock signal; and deactivating the preceding state holding means in response to the activation of the state holding means in the subsequent stage.

Claim 17

An operating method for a serial selection circuit in a semiconductor memory device, said serial selection circuit comprising: a plurality of selecting lines each connected to a memory cell for selecting a memory cell to be accessed; and a plurality of state holding means for respectively holding the state of each of said plurality of selecting lines, said method comprising the steps of: sequentially activating said plurality of state holding means in response to an externally applied clock signal; and deactivating the preceding state holding means in response to the activation of the state holding means in the subsequent stage.

Claim 18

The operating method for a serial selection circuit in a semiconductor memory device according to claim 11, wherein said step of sequentially activating said plurality of state holding means comprises the steps of: generating an activation potential for activating said plurality of state holding means in response to said externally applied clock signal; and applying the activation potential to the state holding means in the subsequent stage in response to the activation of the state holding means in the preceding stage.

Claim 19

The operating method for a serial selection circuit in a semiconductor memory device according to claim 11, wherein said step of deactivating said state holding means in the preceding stage comprises the steps of: delaying said externally applied clock signal; generating a deactivation potential for deactivating said plurality of state holding means in response to the delayed clock signal; and applying the deactivation potential to the state holding means in the preceding stage in response to the activation of the state holding means in the subsequent stage.

Claim 20

A semiconductor memory device capable of sequentially selecting a plurality of memory cells comprising: a plurality of selecting lines each connected to said plurality of memory cells for selecting a connected memory cell; a plurality of flipflop means each connected to said plurality of selecting lines; means for receiving an externally applied clock signal; set means each connected to said plurality of flipflop means, and responsive to an output signal generated from an adjoining flipflop means in the preceding stage and the externally applied clock signal for sequentially setting the flipflop means subsequent thereto; delay means for delaying said externally applied clock signal; and reset means each connected to said plurality of flipflop means, and responsive to the delayed clock signal for resetting the flipflop means set by said set means.

Claim 21

A semiconductor memory device capable of sequentially selecting a plurality of memory cells comprising: a plurality of selecting lines each connected to said plurality of memory cells for selecting a connected memory cell; a plurality of flipflop means each connected to said plurality of selecting lines; means for receiving an externally applied clock signal; set means each connected to said plurality of flipflop means, and responsive to an output signal generated from an adjoining flipflop means in the preceding stage and the externally applied clock signal for sequentially setting the flipflop means subsequent thereto; delay means for delaying said externally applied clock signal; and reset means each connected to said plurality of flipflop means, and responsive to the delayed clock signal for resetting the flipflop means set by said set means.