Patent US1877341A successfully refreshed from Google Patents.
US5293084A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High speed logic circuit
Assignee: Hitachi Ltd
•
Filing: 1992-09-09
•
Granted: 1994-03-08
•
Expires: 2012-09-09
Abstract
Abstract In a high speed logic circuit using a vertical hetero-junction bipolar transistor, in which two-dimensional carriers formed at a semiconductor hetero-junction interface are used as a base layer, the uppermost layer being a collector layer, the lowest layer being an emitter layer, two base electrodes making contact with the base layer are disposed so as to put a collector electrode, which is electrically in contact with the collector layer, therebetween. The base electrodes are used at the same time as a source electrode and a drain electrode, respectively, of a field effect transistor using the two-dimensional carriers as an active layer. The high speed logic circuit is so constructed that one of the base electrodes of the bipolar transistor is an input terminal; the other is connected with a power supply; the emitter is grounded; and the collector is an output terminal.
Inventors
- 👤 Hiroyuki Itoh
- 👤 Toshiyuki Usagawa
- 👤 Atsushi Takai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 20:16
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/09403; H03K19/09418; H03K17/00; H03K17/51; H03K17/56; H03K17/567; H10; H10D; H10D10/00; H10D10/80; H10D10/821; H10D10/841; H10D84/00; H10D84/01; H10D84/02; H10D84/05; H10D86/00; H10D86/01
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
129 words
A high speed logic circuit comprising: a vertical hetero-junction bipolar transistor, in which two-dimensional carriers formed at a semiconductor hetero-junction interface are used as a base layer, the uppermost layer being a collector layer, the lowest layer being an emitter layer; and wherein said bipolar transistor has two base electrodes making contact with the base layer, putting a collector electrode on said collector layer horizontally therebetween, and said base electrodes are used at the same time as a source electrode and a drain electrode, respectively, of a field effect transistor using said two-dimensional carriers as an active layer, one of the base electrodes of said bipolar transistor being an input terminal, the other being connected with a power supply, the emitter being grounded, the collector being an output terminal.
Claim 2
Dependent Claim
129 words
A high speed logic circuit comprising: a vertical hetero-junction bipolar transistor, in which two-dimensional carriers formed at a semiconductor hetero-junction interface are used as a base layer, the uppermost layer being a collector layer, the lowest layer being an emitter layer; and wherein said bipolar transistor has two base electrodes making contact with the base layer, putting a collector electrode on said collector layer horizontally therebetween, and said base electrodes are used at the same time as a source electrode and a drain electrode, respectively, of a field effect transistor using said two-dimensional carriers as an active layer, one of the base electrodes of said bipolar transistor being an input terminal, the other being connected with a power supply, the emitter being grounded, the collector being an output terminal.
Claim 3
Dependent Claim
48 words
A high speed logic circuit according to claim 1, wherein said bipolar transistor is of pnp type, the power supply connected with the other base electrode is negative, and an absolute value thereof is greater than a voltage between the base and the emitter of said bipolar transistor.
Claim 4
Dependent Claim
27 words
A high speed logic circuit according to claim 2, wherein the junction between the base and the emitter of said bipolar transistor is constituted by a hetero-junction.
Claim 5
Dependent Claim
156 words
A high speed logic circuit comprising: a vertical hetero-junction bipolar transistor, in which two-dimensional carriers formed at a semiconductor hetero-junction interface are used as a base layer, the uppermost layer being a collector layer, the lowest layer being an emitter layer; and wherein said bipolar transistor has two base electrodes contacted with said base layer, putting a collector electrode therebetween; a field effect transistor using said two-dimensional carriers as an active layer is formed, one of the base electrodes being a drain electrode, the other being a source electrode, said collector electrode being a gate electrode; the emitter of said bipolar transistor is grounded; said one of the base electrodes serves as an input; an output is taken out from said collector; and said field effect transistor is used as an injector, said other base electrode used at the same time as the source electrode of said field effect transistor being connected with a power supply.
Claim 6
Dependent Claim
156 words
A high speed logic circuit comprising: a vertical hetero-junction bipolar transistor, in which two-dimensional carriers formed at a semiconductor hetero-junction interface are used as a base layer, the uppermost layer being a collector layer, the lowest layer being an emitter layer; and wherein said bipolar transistor has two base electrodes contacted with said base layer, putting a collector electrode therebetween; a field effect transistor using said two-dimensional carriers as an active layer is formed, one of the base electrodes being a drain electrode, the other being a source electrode, said collector electrode being a gate electrode; the emitter of said bipolar transistor is grounded; said one of the base electrodes serves as an input; an output is taken out from said collector; and said field effect transistor is used as an injector, said other base electrode used at the same time as the source electrode of said field effect transistor being connected with a power supply.
Claim 7
Dependent Claim
31 words
A high speed logic circuit according to claim 4, wherein the gate of said field effect transistor is controlled by an output taken out from the collector of said bipolar transistor.
Claim 8
Dependent Claim
143 words
A semiconductor device comprising: a semi-insulating substrate; a first semiconductor layer formed on said semi-insulating substrate and having a first conductivity type; a second semiconductor layer formed on said first semiconductor layer and having a second conductivity type; a third semiconductor layer formed on a part of said second semiconductor layer and having the first conductivity type; a first electrode connected electrically with said first semiconductor layer; a pair of second electrodes disposed so as to put said third semiconductor layer therebetween and connected electrically with said second semiconductor layer; and a third electrode connected electrically with said third semiconductor layer; and wherein said first electrode is connected with a first power supply, and one of said second electrodes is connected with a second power supply, a signal being inputted through the other of said second electrodes and outputted from said third electrode.
Claim 9
Dependent Claim
143 words
A semiconductor device comprising: a semi-insulating substrate; a first semiconductor layer formed on said semi-insulating substrate and having a first conductivity type; a second semiconductor layer formed on said first semiconductor layer and having a second conductivity type; a third semiconductor layer formed on a part of said second semiconductor layer and having the first conductivity type; a first electrode connected electrically with said first semiconductor layer; a pair of second electrodes disposed so as to put said third semiconductor layer therebetween and connected electrically with said second semiconductor layer; and a third electrode connected electrically with said third semiconductor layer; and wherein said first electrode is connected with a first power supply, and one of said second electrodes is connected with a second power supply, a signal being inputted through the other of said second electrodes and outputted from said third electrode.
Claim 10
Dependent Claim
37 words
A semiconductor device according to claim 6, wherein a junction between said first semiconductor layer and said second semiconductor layer constitutes a hetero-junction having two-dimensional carriers formed on said second semiconductor layer side of said junction interface.
Claim 11
Dependent Claim
46 words
A semiconductor device according to claim 7, wherein said two-dimensional carriers constitute the base layer of a transistor driven by using the other of said second electrodes as the base electrode, said first electrode as the emitter electrode and said third electrode as the collector electrode.
Claim 12
Dependent Claim
49 words
A semiconductor device according to claim 8, wherein said two-dimensional carriers act further at the same time as a channel layer of a field effect transistor driven by using said third electrode as the gate electrode and said second electrodes as the source electrode and the drain electrode, respectively.
Claim 13
Dependent Claim
36 words
A semiconductor device according to claim 7, further comprising an isolating region isolating different semiconductor layers between said first semiconductor layer and said second semiconductor layer except for a lower part of said third semiconductor layer.
Claim 14
Dependent Claim
23 words
A semiconductor device according to claim 7, wherein a junction between said second semiconductor layer and said third semiconductor layer constitutes a hetero-junction.
Claim 15
Dependent Claim
26 words
A semiconductor device according to claim 6, wherein said first, said second and said third semiconductor layer are formed by epitaxial growth using molecular beam epitaxy.
Claim 16
Dependent Claim
28 words
A semiconductor device according to claim 6, wherein said first, said second and said third semiconductor layer are formed by epitaxial growth using metal organic chemical vapor deposition.
Claim 17
Dependent Claim
83 words
A high speed logic circuit comprising: an input node, through which a logic signal is inputted; an output node, through which a logic signal is outputted; a bipolar transistor having a base connected with said input node, an emitter connected with a ground potential, and a collector connected with said output node; and a field effect transistor having a gate connected with a collector of said transistor, drain connected with a base of said transistor, and a source connected with a power supply.
Claim 18
Dependent Claim
83 words
A high speed logic circuit comprising: an input node, through which a logic signal is inputted; an output node, through which a logic signal is outputted; a bipolar transistor having a base connected with said input node, an emitter connected with a ground potential, and a collector connected with said output node; and a field effect transistor having a gate connected with a collector of said transistor, drain connected with a base of said transistor, and a source connected with a power supply.
Claim 19
Dependent Claim
74 words
A semiconductor device according to claim 14, wherein said bipolar transistor is a vertical bipolar transistor, in which the uppermost layer is a collector layer and the lowest layer is an emitter layer, and a junction between a semiconductor layer forming said emitter layer and a semiconductor layer formed between said emitter layer and said collector layer is constituted by a hetero-junction, two-dimensional carriers formed at the hetero-junction interface acting as a base layer.
Claim 20
Dependent Claim
25 words
A semiconductor device according to claim 15, wherein said base layer acts at the same time as a channel layer of said field effect transistor.
Claim 21
Dependent Claim
32 words
A semiconductor device according to claim 15, wherein a junction between said collector layer and said semiconductor layer formed between said emitter layer and said collector layer is constituted by a hetero-junction.
Claim 22
Dependent Claim
24 words
A semiconductor device according to claim 14, wherein said field effect transistor acts as an injector supplying carriers to the base of said transistor.
Claim 23
Dependent Claim
29 words
A semiconductor device according to claim 18, wherein the gate of said field effect transistor is controlled by an output taken out from the collector of said bipolar transistor.
References Cited (Backward Citations)
US4821090A
Cited
US5151618A
Cited
JPS62199049A
Cited
US4779014A
Cited
JPS63236358A
Cited
US5012318A
Cited
US5206546A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-03-07 | 1997-09-06 | 1998-03-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-03-07 | 2001-09-06 | 2002-03-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-03-07 | 2005-09-06 | 2006-03-08 | $7700.00 | Window Closed / Lapsed |