Patent US5291046A successfully refreshed from Google Patents.
US5291046A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory device
Assignee: Fujitsu Ltd
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Filing: 1992-02-06
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Granted: 1994-03-01
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Expires: 2012-02-06
Abstract
Abstract A control gate formed on top of an insulation layer over a floating gate for a transistor element of a memory cell in a redundancy ROM is shaped in a form covering not only the top but also the sides of the floating gate. A drain electrode wiring conventionally connected through a well is directly connected to a drain diffusion area. This enables the redundancy ROM to be miniaturized and the voltage fall at the edge of a drain diffusion area to be reduced.
Inventors
- 👤 Sinsuke Kumakura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 04:59
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0416
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
243 words
A semiconductor memory device whose memory cell is a transistor element, comprising: a source area and a drain area formed on the surface of a semiconductor substrate; a floating gate provided on top of a first insulation layer over the area between said source area and said drain area; a control gate provided on top of a second insulation layer over the top and sides of the floating gate such that said control gate prevents intrusion of a ray of light into said floating gate; a first wiring layer forming an electrode wiring of one of said source area or said drain area by contacting said one of said source area or said drain area, said first wiring layer being arranged to define a blind coating by extending over a third insulation layer covering said control gate; and a second wiring layer provided on top of said third insulation layer and electrically isolated from said first wiring layer, a part of said second wiring layer contacting the other of said drain area or said source area, wherein a gap between said first wiring layer and said second wiring layer is positioned above either said source area or said drain area, and said control gate is positioned between said gap and said floating gate and extends over the top and sides of said floating gate such that said control gate prevents a ray of light passing through said gap from striking said floating gate.
Claim 2
Dependent Claim
243 words
A semiconductor memory device whose memory cell is a transistor element, comprising: a source area and a drain area formed on the surface of a semiconductor substrate; a floating gate provided on top of a first insulation layer over the area between said source area and said drain area; a control gate provided on top of a second insulation layer over the top and sides of the floating gate such that said control gate prevents intrusion of a ray of light into said floating gate; a first wiring layer forming an electrode wiring of one of said source area or said drain area by contacting said one of said source area or said drain area, said first wiring layer being arranged to define a blind coating by extending over a third insulation layer covering said control gate; and a second wiring layer provided on top of said third insulation layer and electrically isolated from said first wiring layer, a part of said second wiring layer contacting the other of said drain area or said source area, wherein a gap between said first wiring layer and said second wiring layer is positioned above either said source area or said drain area, and said control gate is positioned between said gap and said floating gate and extends over the top and sides of said floating gate such that said control gate prevents a ray of light passing through said gap from striking said floating gate.
Claim 3
Dependent Claim
23 words
The semiconductor memory device according to claim 1, wherein: said insulation layer provided under said floating gate is made of an oxide film.
Claim 4
Dependent Claim
23 words
The semiconductor memory device according to claim 1, wherein: said insulation layer provided under said floating gate is made of a nitride film.
Claim 5
Dependent Claim
34 words
The semiconductor memory device according to claim 1, wherein: carriers are stored in said floating gate by injecting into said floating gate hot carriers generated by an avalanche breakdown occurring near said drain area.
Claim 6
Dependent Claim
34 words
The semiconductor memory device according to claim 2, wherein: carriers are stored in said floating gate by injecting into said floating gate hot carriers generated by an avalanche breakdown occurring near said drain area.
Claim 7
Dependent Claim
34 words
The semiconductor memory device according to claim 3, wherein: carriers are stored in said floating gate by injecting into said floating gate hot carriers generated by an avalanche breakdown occurring near said drain area.
Claim 8
Dependent Claim
39 words
The semiconductor memory device according to claim 1, wherein: carriers are stored in and emitted from said floating gate by tunnel currents flowing from said floating gate to said drain area through said insulation layer under said floating gate.
Claim 9
Dependent Claim
39 words
The semiconductor memory device according to claim 2, wherein: carriers are stored in and emitted from said floating gate by tunnel currents flowing from said floating gate to said drain area through said insulation layer under said floating gate.
Claim 10
Dependent Claim
39 words
The semiconductor memory device according to claim 3, wherein: carriers are stored in and emitted from said floating gate by tunnel currents flowing from said floating gate to said drain area through said insulation layer under said floating gate.
Claim 11
Dependent Claim
195 words
A semiconductor memory device whose memory cell is a transistor element, comprising: a source area and a drain area formed on the surface of a semiconductor substrate; a floating gate provided on top of a first insulation layer over the area between said source area and said drain area; a control gate provided on top of a second insulation layer over the top and sides of the floating gate such that said control gate prevents intrusion of a ray of light into said floating gate; a first wiring layer forming an electrode wiring of one of said source area or said drain area by contacting said one of said source area or said drain area, said first wiring layer being arranged to define a blind coating by extending over a third insulation layer covering said control gate; and a second wiring layer provided on top of said third insulation layer and electrically isolated from said first wiring layer, a part of said second wiring layer contacting the other of said drain area or said source area, wherein a gap between said first wiring layer and said second wiring layer is positioned above said control gate.
Claim 12
Dependent Claim
195 words
A semiconductor memory device whose memory cell is a transistor element, comprising: a source area and a drain area formed on the surface of a semiconductor substrate; a floating gate provided on top of a first insulation layer over the area between said source area and said drain area; a control gate provided on top of a second insulation layer over the top and sides of the floating gate such that said control gate prevents intrusion of a ray of light into said floating gate; a first wiring layer forming an electrode wiring of one of said source area or said drain area by contacting said one of said source area or said drain area, said first wiring layer being arranged to define a blind coating by extending over a third insulation layer covering said control gate; and a second wiring layer provided on top of said third insulation layer and electrically isolated from said first wiring layer, a part of said second wiring layer contacting the other of said drain area or said source area, wherein a gap between said first wiring layer and said second wiring layer is positioned above said control gate.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-02-28 | 1997-08-30 | 1998-03-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-02-28 | 2001-08-30 | 2002-03-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-02-28 | 2005-08-30 | 2006-03-01 | $7700.00 | Window Closed / Lapsed |