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US5289424A
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Pseudo-static random access memory
Assignee: Sharp Corp
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Filing: 1992-08-25
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Granted: 1994-02-22
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Expires: 2012-08-25
Abstract
Abstract In a pseudo-static random access memory of the invention, refresh operations are conducted in a normal mode and a self-refresh mode. The memory includes a plurality of bit-line pairs each having two bit lines, a precharge voltage generating circuit for precharging the plurality of bit-line pairs to a first potential level during a precharge period in the normal mode, the circuit being electrically connected to the plurality of bit-line pairs during the precharge period in the normal mode; and bit line discharge circuit for discharging the bit-line pairs during a precharge period in the self-refresh mode, thereby decreasing the potential level of the bit-line pairs to a second potential level which is below the first potential level.
Inventors
- 👤 Nobuhiko Ito
- 👤 Makoto Ihara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 13:54
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4094; G11C11/406
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
115 words
A pseudo-static random access memory in which refresh operations are conducted in a normal mode and a self-refresh mode, the memory comprising: a plurality of bit-line pairs each having two bit lines; a precharge voltage generating circuit for precharging the plurality of bit-line pairs to a first potential level during a precharge period in the normal mode, the circuit being electrically connected to the plurality of bit-line pairs during the precharge period in the normal mode; and bit line discharge means for discharging the bit-line pairs during a precharge period in the self-refresh mode, thereby decreasing the potential level of the bit-line pairs to a second potential level which is below the first potential level.
Claim 2
Dependent Claim
115 words
A pseudo-static random access memory in which refresh operations are conducted in a normal mode and a self-refresh mode, the memory comprising: a plurality of bit-line pairs each having two bit lines; a precharge voltage generating circuit for precharging the plurality of bit-line pairs to a first potential level during a precharge period in the normal mode, the circuit being electrically connected to the plurality of bit-line pairs during the precharge period in the normal mode; and bit line discharge means for discharging the bit-line pairs during a precharge period in the self-refresh mode, thereby decreasing the potential level of the bit-line pairs to a second potential level which is below the first potential level.
Claim 3
Dependent Claim
33 words
A pseudo-static random access memory according to claim 1, further comprising: first switch means for disconnecting the bit-line pairs from the discharge voltage generating circuit during the precharge period in the self-refresh mode.
Claim 4
Dependent Claim
37 words
A pseudo-static random access memory according to claim 2, further comprising: second switch means for electrically shorting the two bit lines of each of the plurality of bit-line pairs during the precharge period in the self-refresh mode.
Claim 5
Dependent Claim
47 words
A pseudo-static random access memory according to claim 2, further comprising: potential level holding means for holding the second potential level of the bit-line pairs at a predetermined or larger value which is lower than the first potential level during the precharge period in the self-refresh mode.
Claim 6
Dependent Claim
49 words
A pseudo-static random access memory according to claim 2, further comprising: potential level fixing means for fixing the second potential level of the bit-line pairs at a predetermined value which is lower than the first potential level at the last portion of the precharge period in the self-refresh mode.
Claim 7
Dependent Claim
21 words
A pseudo-static random access memory according to claim 2, wherein the first potential level is half of a supply voltage level.
References Cited (Backward Citations)
US5047985A
Cited
US5083047A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-02-21 | 1997-08-23 | 1998-02-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-02-21 | 2001-08-23 | 2002-02-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-02-21 | 2005-08-23 | 2006-02-22 | $7700.00 | Window Closed / Lapsed |