US5289418A
Expired / Lapsed
US
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Memory apparatus with built-in parity generation
Assignee: Extended Systems Inc
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Filing: 1992-02-14
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Granted: 1994-02-22
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Expires: 2012-02-14
Abstract
Abstract The present invention provides a dedicated memory circuit which supports the generation of parity data in connection with the storing of data. This improved memory circuit allows the parity generation to be done remotely from the CPU while consuming less time. The memory array is provided with its data output being connected to combinational logic. Another input to combinational logic is for external data. The data already in the array and the new data are combined to the combinational logic, preferably an exclusive-or arrangement, to produce the parity data which is then returned to the memory array. A latch is provided between the exclusive-or logic and the memory array data lines to allow isolation of the data during the two cycles of the read out of the array and the right back to the array after the exclusive-or.
Inventors
- 👤 Al Youngerth
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 06:47
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1076; G06F2211/00; G06F2211/10; G06F2211/1002; G06F2211/1054
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
156 words
A memory circuit comprising: a memory array for storing a plurality of bits, said memory array having address inputs and data input and output lines; a logic circuit having first inputs coupled to said memory array data output lines and second inputs coupled to external data input/output lines; latching means, coupled between an output of said logic circuit and said memory array data input lines; transceiver means, coupled between said memory array data input lines and output lines and said external data input/output lines, for disabling the flow of data between said external data input/output lines and said memory array data input lines and output lines in response to a transceiver disable control signal; and control means, having an external control input for receiving an exclusive write signal and a transceiver control output coupled to said transceiver means, for providing said transceiver disable control signal to said transceiver means in response to said exclusive write signal.
Claim 2
Dependent Claim
156 words
A memory circuit comprising: a memory array for storing a plurality of bits, said memory array having address inputs and data input and output lines; a logic circuit having first inputs coupled to said memory array data output lines and second inputs coupled to external data input/output lines; latching means, coupled between an output of said logic circuit and said memory array data input lines; transceiver means, coupled between said memory array data input lines and output lines and said external data input/output lines, for disabling the flow of data between said external data input/output lines and said memory array data input lines and output lines in response to a transceiver disable control signal; and control means, having an external control input for receiving an exclusive write signal and a transceiver control output coupled to said transceiver means, for providing said transceiver disable control signal to said transceiver means in response to said exclusive write signal.
Claim 3
Dependent Claim
55 words
The memory circuit of claim 1 wherein said control means further comprises a read input line and a write input line, said control means generating a transceiver enable control signal on said transceiver control output in response to a read signal on said read input line or a write signal on said write input line.
Claim 4
Dependent Claim
130 words
A memory circuit for generating block parity from multiple bytes of data comprising: a memory array for storing a plurality of bits, said memory array having address inputs and data input and output lines; a logic circuit having first inputs coupled to said memory array data output lines for receiving a first data byte and second inputs coupled to external data input lines for receiving a second data byte, said logic circuit producing a parity byte from the combination of said first and second data bytes; and latching means, coupled between an output of said logic circuit and said memory array data input lines, for isolating said parity byte from said first and second data bytes; whereby parity generation is done with said memory circuit remotely from an external processor.
Claim 5
Dependent Claim
130 words
A memory circuit for generating block parity from multiple bytes of data comprising: a memory array for storing a plurality of bits, said memory array having address inputs and data input and output lines; a logic circuit having first inputs coupled to said memory array data output lines for receiving a first data byte and second inputs coupled to external data input lines for receiving a second data byte, said logic circuit producing a parity byte from the combination of said first and second data bytes; and latching means, coupled between an output of said logic circuit and said memory array data input lines, for isolating said parity byte from said first and second data bytes; whereby parity generation is done with said memory circuit remotely from an external processor.
Claim 6
Dependent Claim
16 words
The memory circuit of claim 3 wherein said logic circuit is an exclusive OR logic circuit.
Claim 7
Dependent Claim
83 words
The memory circuit of claim 3 further comprising control means, having an external exclusive write control input and a control output line coupled to said latching means, for allowing data from said memory array data output lines to be combined with data from said external data input lines in said logic circuit during a first cycle to produce combined data and enabling an output of said combined data in said latching means to said memory array data input lines in a second cycle.
Claim 8
Dependent Claim
23 words
The memory circuit of claim 3 wherein said memory array data input lines and data output lines are the same data input/output lines.
Claim 9
Dependent Claim
17 words
The memory circuit of claim 3 wherein said memory circuit is contained on a single semiconductor chip.
Claim 10
Dependent Claim
111 words
The memory circuit of claim 3 wherein said external data input lines are external data input/output lines, and further comprising: transceiver means, coupled between said memory array data input lines and output line and said external data input/output lines, for disabling the flow of data between said external data input/output lines and said memory array data input lines and output lines in response to a transceiver disable control signal; and control means, having an external control input for receiving an exclusive write signal and a transceiver control output coupled to said transceiver means, for providing said transceiver disable control signal to said transceiver means in response to said exclusive write signal.
Claim 11
Dependent Claim
55 words
The memory circuit of claim 8 wherein said control means further comprises a read input line and a write input line, said control means generating a transceiver enable control signal on said transceiver control output in response to a read signal on said read input line or a write signal on said write input line.
Claim 12
Dependent Claim
143 words
A memory circuit comprising: a memory array for storing a plurality of bits, said memory array having address inputs and data input/output lines; an exclusive OR logic circuit having first inputs coupled to said memory array data input/output lines and second inputs coupled to external data input/output lines; latching means, coupled between an output of said logic circuit and said memory array data input/output lines; and control means, having an external exclusive write control input and a control output line coupled to said latching means, for allowing data from said memory array data input/output lines to be combined with data from said external data input/output lines in said exclusive OR logic circuit during a first cycle to produce combined data and enabling an output of said combined data in said latching means to said memory array data input lines in a second cycle.
Claim 13
Dependent Claim
143 words
A memory circuit comprising: a memory array for storing a plurality of bits, said memory array having address inputs and data input/output lines; an exclusive OR logic circuit having first inputs coupled to said memory array data input/output lines and second inputs coupled to external data input/output lines; latching means, coupled between an output of said logic circuit and said memory array data input/output lines; and control means, having an external exclusive write control input and a control output line coupled to said latching means, for allowing data from said memory array data input/output lines to be combined with data from said external data input/output lines in said exclusive OR logic circuit during a first cycle to produce combined data and enabling an output of said combined data in said latching means to said memory array data input lines in a second cycle.
Claim 14
Dependent Claim
265 words
A memory circuit comprising: a memory array for storing a plurality of bits, said memory array having address inputs and data input/output lines; an exclusive OR logic circuit having first inputs coupled to said memory array data input/output lines and second inputs coupled to external data input/output lines; latching means, coupled between an output of said logic circuit and said memory array data input/output lines; transceiver means, coupled between said memory array data input/output lines and said external data input/output lines, for disabling the flow of data between said external data input/output lines and said memory array data input/output lines in response to a transceiver disable control signal; and control means, having an external exclusive write control input and a control output line coupled to said latching means, for allowing data from said memory array data input/output lines to be combined with data from said external data input/output lines in said exclusive OR logic circuit during a first cycle to produce combined data and enabling an output of said combined data in said latching means to said memory array data input/output lines in a second cycle; said control means having a transceiver control output coupled to said transceiver means for providing said transceiver disable control signal to said transceiver means in response to said exclusive write signal; said control means further comprising a read input line and a write input line, said control means generating a transceiver enable control signal on said transceiver control output in response to a read signal on said read input line or a write signal on said write input line.
Claim 15
Dependent Claim
265 words
A memory circuit comprising: a memory array for storing a plurality of bits, said memory array having address inputs and data input/output lines; an exclusive OR logic circuit having first inputs coupled to said memory array data input/output lines and second inputs coupled to external data input/output lines; latching means, coupled between an output of said logic circuit and said memory array data input/output lines; transceiver means, coupled between said memory array data input/output lines and said external data input/output lines, for disabling the flow of data between said external data input/output lines and said memory array data input/output lines in response to a transceiver disable control signal; and control means, having an external exclusive write control input and a control output line coupled to said latching means, for allowing data from said memory array data input/output lines to be combined with data from said external data input/output lines in said exclusive OR logic circuit during a first cycle to produce combined data and enabling an output of said combined data in said latching means to said memory array data input/output lines in a second cycle; said control means having a transceiver control output coupled to said transceiver means for providing said transceiver disable control signal to said transceiver means in response to said exclusive write signal; said control means further comprising a read input line and a write input line, said control means generating a transceiver enable control signal on said transceiver control output in response to a read signal on said read input line or a write signal on said write input line.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-02-21 | 1997-08-23 | 1998-02-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-02-21 | 2001-08-23 | 2002-02-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-02-21 | 2005-08-23 | 2006-02-22 | $7700.00 | Window Closed / Lapsed |