Data coupling arrangement

Claim 2

A data coupling arrangement comprising: A. a plurality of data input circuits for, in parallel, each successively receiving nibbles of respective data words, each nibble having a value; B. a selective coupling circuit for selectively coupling nibbles from one of said data input circuits as identified by an input circuit identifier to an output; C. an input identifier control circuit for generating the input circuit identifier having a selected condition to control said selective coupling circuit in response to a selected relationship between values represented by said nibbles to thereby control transfer of nibbles from said data input circuits to the output; and D. a latch control circuit for, in response to receipt by said data input circuits of nibbles whose values differ, enabling said input identifier circuit to thereafter maintain its condition, thereby enabling said selective coupling circuit to thereafter transfer the nibbles subsequently received by same data input circuit to the output.

Claim 3

A data coupling arrangement as defined in claim 1 in which said input identifier control circuit includes: A. a comparator circuit for generating a nibble comparison signal indicating a relative value of nibbles contemporaneously received by said data input circuits; and B. a latch circuit connected to said comparator circuit and said latch control circuit for generating said input circuit identifier in response to said nibble comparison signal under control of said latch control circuit.

Claim 4

A data coupling arrangement as defined in claim 2 in which: A. the latch control circuit generates a latch control signal (i) having an initial pass state when the initial nibbles of a data word contemporaneously received by the data input circuits have the same value, and (ii) switching to a latch state when said latch control circuit determines that the nibbles contemporaneously received by the data input circuits have differing values, the latch control circuit maintaining the latch control signal in the latch state through the last nibble comprising the date word, and B. said latch circuit generates said input circuit identifier: (i) to correspond to the nibble comparison signal generated by the comparator circuit while the latch control signal is in the pass state, and (ii) to hold the nibble comparison signal generated by the comparator circuit when the latch control signal switches to the latch state, the latch circuit maintaining the nibble comparison signal while the latch control signal is in the latch state.

Claim 5

A data coupling arrangement as defined in claim 3 in which said latch circuit comprises: A. a flip-flop circuit for receiving and latching the input circuit identifier, the flip-flop circuit generating an output signal corresponding to the latched input circuit identifier; and B. a multiplexer connected to said comparator, said flip-flop circuit, and said latch control circuit, the multiplexer coupling as the input circuit identifier: (i) the signal from the comparator while the latch control signal is in the pass state, and (ii) the output signal from the flip-flop circuit while the latch control signal is in the latch state.

Claim 6

A data coupling arrangement as defined in claim 4 in which said multiplexer is further connected to couple an initialization signal to the flip-flop circuit when the latch control signal is in a disable state.

Claim 7

A data coupling arrangement as defined in claim 2 in which each nibble of each input data word comprises a predetermined number of data bits, the data bits of each nibble being organized in a series of bit positions representing a value ordering, the comparator circuit including: A. a first stage comprising a series of input decoders each associated with a bit position for receiving the data bits in respective bit positions from the data input circuits, each input decoder asserting a "greater than" output signal if the data bit received from a predetermined one of said data input circuits has a value greater than the value of the data bit received from the other of said data input circuit, and asserting a "not less than" output signal if the data bit from the predetermined data input circuit has a value not less than the value of the data bit received from the other data input circuit; B. a second stage comprising: (i) a series of relative value resolution circuits each associated with a bit position other than the highest-ordered bit position, each relative value resolution circuit asserting a bit position order "greater than" signal if the "not less than" output signal from input decoders associated with higher-ordered bit positions is asserted and the "greater than" output signal from an input decoder associated with its bit position is also asserted; and (ii) a "not less than" value resolution circuit for generating a nibble "not less than" signal indicating that the "not less than" signals from all of the input decoders are asserted, and C. a third stage for generating the nibble comparison signal in response to the "greater than" output signal from the input decoder associated with the highest-order bit position, the bit position order "greater than" signals from all of the relative value resolution circuits and the nibble "not less than" signal from the "not less than" value resolution circuit.

Claim 8

A data coupling arrangement as defined in claim 1 in which each nibble of each data word includes a plurality of data bits, said latch control circuit comprising: A. bit-wise comparison circuit for comparing asserting an equals signal if corresponding data bits of the data words received by the data input circuit have the same value; and B. a latch circuit for generating a latch control signal (i) corresponding to the equals signal from the bit-wise comparison signal when the equals signal initially indicates that the nibbles of a data word contemporaneously received by the data input circuits have the same value, and (ii) latching the equals signal from said bit-wise comparison circuit when the equals signal indicates that determines that the nibbles contemporaneously received by the data input circuits have differing values, the latch circuit maintaining the latch control signal through the last nibble comprising the date word.

Claim 9

A data coupling arrangement as defined in claim 7 in which said bit-wise comparison circuit includes: A. an exclusive-OR gate circuit for receiving corresponding bits from said data input circuits and generating, for each bit position, a bit value correspondence signal having an asserted condition if the bits have different values, and a negated condition if the bits have the same value; B. a complement circuit for generating complement bit value correspondence signals having values representative of the complements of respective bit value correspondence signals from the exclusive-OR circuit and C. a coincident circuit for generating the latch control signal having an asserted condition if all of the complement bit value correspondence signals are asserted, and otherwise generating the latch control signal to have a negated condition.

Claim 10

A data coupling arrangement as defined in claim 7 in which said latch circuit comprises: A. a flip-flop circuit for receiving and latching a selected correspondence signal generating, in response, a latched selected correspondence signal; and B. a multiplexer connected to said bit-wise comparison circuit and said flip-flop circuit, the multiplexer coupling as the selected correspondence signal to the flip-flop circuit: (i) the signal from the bit-wise comparison circuit while the latched selected correspondence signal control signal is asserted; and (ii) the latched selected correspondence signal from the flip-flop circuit while the latched selected correspondence signal is negated.

Claim 11

A data coupling arrangement as defined in claim 9 in which: A. said multiplexer is further connected to couple an initialization signal for storage in the flip-flop circuit, and B. said arrangement further includes a multiplexer control circuit connected to said flip-flop circuit and said multiplexer, the multiplexer control circuit receiving the latched selected correspondence signal from the flip-flop circuit and an enable control signal and generating in response a multiplexer control signal for controlling the multiplexer, the multiplexer control signal enabling the multiplexer to couple: (i) the signal from the bit-wise comparison circuit while the latched selected correspondence signal control signal and enable signal are asserted; (ii) the latched selected correspondence signal from the flip-flop circuit while the latched selected correspondence signal is negated and the enable signal is asserted; and (iii) the initialization signal while the enable signal is negated.