Transmit/receive switch for phased array antenna

Claim 2

A transmit/receive switch comprising: a control signal coupled to a control input of said transmit/receive switch for selectively placing said switch in one of two modes, a first state of said control signal selecting a transmit mode of said switch and a second state of said control signal selecting a receive mode of said switch; network means coupled to an input port of said switch for providing a termination impedance to match a source impedance of an RF input signal coupled to said input port in response to said first state of said control signal, said transmit/receive switch providing a phase delay in a range of 30 degrees to 60 degrees to said RF input signal; and means coupled between said control input and said network means for electrically disconnecting said termination impedance in response to said second state of said control signal, thereby enabling said RF input signal to pass through said transmit/receive switch.

Claim 3

The transmit/receive switch as recited in claim 1 wherein: said network means comprises an input branch having a resistor and a capacitor in parallel, one end of said parallel resistor and capacitor being coupled to said input signal at said input port; said electrically disconnecting means comprises a first switching means coupled between the other end of said parallel resistor and capacitor and ground for enabling said transmit mode of operation of said transmit/receive switch in accordance with the first state of said control signal being coupled to said control input of said transmit/receive switch; said electrically disconnecting means further comprises a second switching means forming an output branch of said network means and coupled between an output port of said transmit/receive switch and ground for enabling said receive mode of operation of said transmit/receive switch in accordance with the second state of said control signal being coupled to said control input of said transmit/receive switch; and a series branch of said network means comprises an inductor coupled between said input port and said output port of said transmit/receive switch.

Claim 4

The transmit/receive switch as recited in claim 2, wherein: said first switching means comprises a first field effect transistor (FET) and said second switching means comprises a second field effect transistor, each FET having source, gate and drain terminals, said control input being coupled to said gate terminal of each field effect transistor, said first FET having said drain terminal thereof connected to said other end of said parallel resistor and capacitor and said source terminal thereof connected to said ground, and said second FET having said drain terminal thereof connected to said output port and said source terminal thereof connected to said ground.

Claim 5

The transmit/receive switch as recited in claim 1 wherein: said network means further comprises a π network means for emulating a one-eighth wavelength transmission line when said phase delay equals approximately 45 degrees, said π network means comprising an input branch means connected to said input port, an output branch means connected to said output port, and a series branch means connected between said input branch means and said output branch means.

Claim 6

The transmit/receive switch as recited in claim 4 wherein: said π network means provides isolation and bandwidth characteristics of a one-quarter wavelength transmission line.

Claim 7

A transmit/receive switch comprising: a π network means for providing a phase delay in a range of 30 degrees to 60 degrees to an input signal at an input port of said switch in accordance with a control signal applied thereto, said π network means comprising an input branch connected to said input port, an output branch connected to an output port of said switch and a series branch connected between said input port and said output port; said input branched of said π network means comprising a resistor and a capacitor in parallel having one end coupled to said input signal at said input port; a first switching means coupled between the other end of said resistor and capacitor in parallel and ground in said input branch for enabling a transmit mode of operation of said transmit/receive switch in accordance with a first state of said control signal being coupled to a control terminal of said first switching means; a second switching means in said output branch of said π network means and coupled between said output port of said π network means and ground for enabling a receive mode of operation of said transmit/receive switch in accordance with a second state of said control signal being coupled to a control terminal of said second switching means; and said series branch of said π network means comprises an inductor coupled between said input port and said output port of said transmit/receive switch.

Claim 8

A transmit/receive switch comprising: a π network means for providing a phase delay in a range of 30 degrees to 60 degrees to an input signal at an input port of said switch in accordance with a control signal applied thereto, said π network means comprising an input branch connected to said input port, an output branch connected to an output port of said switch and a series branch connected between said input port and said output port; said input branched of said π network means comprising a resistor and a capacitor in parallel having one end coupled to said input signal at said input port; a first switching means coupled between the other end of said resistor and capacitor in parallel and ground in said input branch for enabling a transmit mode of operation of said transmit/receive switch in accordance with a first state of said control signal being coupled to a control terminal of said first switching means; a second switching means in said output branch of said π network means and coupled between said output port of said π network means and ground for enabling a receive mode of operation of said transmit/receive switch in accordance with a second state of said control signal being coupled to a control terminal of said second switching means; and said series branch of said π network means comprises an inductor coupled between said input port and said output port of said transmit/receive switch.

Claim 9

The transmit/receive switch as recited in claim 6 wherein: said first switching means comprises a first field effect transistor (FET) and said second switching means comprises a second field effect transistor, each FET having a source, gate and drain terminals, said control terminal of each switching means being realized by the gate terminal of each FET, said control signal being coupled to said gate terminal of each field effect transistor, said first FET having said drain terminal thereof connected to said other end of said parallel resistor and capacitor and said source terminal thereof connected to said ground, and said second FET having said drain terminal thereof connected to said output port and said source terminal thereof connected to said ground.

Claim 10

The transmit/receive switch as recited in claim 6 wherein: said π network means having electrical characteristics of a one-eighth wavelength transmission line when said phase delay equals approximately 45 degrees.

Claim 11

The transmit/receive switch as recited in claim 8 wherein: said π network means provides isolation and bandwidth characteristics of a one-quarter wavelength transmission line.

Claim 12

The transmit/receive switch as recited in claim 6 wherein: said capacitor of said input branch having a capacitive resistance with cancels out an inductive reactance associated with said inductor to minimize transmit signal reflectance.

Claim 15

The method as recited in claim 11 wherein: said step of providing said π network means further comprises the steps of emulating a one-eighth wavelength transmission line when said phase delay equals approximately 45 degrees and exhibiting isolation and bandwidth characteristics of a one-quarter wavelength transmission line.

Claim 18

The method as recited in claim 13 wherein said step of electrically connecting said termination impedance comprises the steps of: providing an input branch of a network means having a resistor and a capacitor in parallel with one end connected to said RF input signal at said input port and a first switching means connected between the other end of said resistor and capacitor in parallel and ground for enabling a transmit mode of operation of said transmit/receive switch in accordance with the state of said control signal connected to said control input; providing an output branch of said network means having a second switching means connected between an output port of said transmit/receive switch and ground for enabling said receive mode of operation of said transmit/receive switch in accordance with the state of said control signal connected to said control input of said second switching means; providing a series branch of said network means having an inductor connected between said input port and said output port of said transmit/receive switch.

Claim 19

The method as recited in claim 13 wherein: said step of electrically connecting termination impedance comprises providing a π network means, said π network means comprising an input branch means coupled to said input port, an output branch means coupled to said output port, and a series branch means coupled between said input port means and said output port, which provides said phase delay in a range of 30 degrees to 60 degrees, further comprises the steps of emulating a one-eighth wavelength transmission line when said phase delay equals approximately 45 degrees, and exhibiting isolation and bandwidth characteristics of a one-quarter wavelength transmission line.