Pulse phase difference encoding circuit

Claim 2

A phase difference detecting circuit for detecting a phase difference between a first signal and a second signal delayed from said first signal by a certain delay time, said circuit comprising: a delayed signal generating means comprising a plurality of serially-connected delay elements having an end delay element connected to a beginning delay element to form a ring circuit, said first signal being input to any one connecting portion formed between any two adjacent delay elements, for sequentially generating a delayed signal at each said connecting portion of each said delay element, said signal being sequentially delayed from one connecting portion to another; position detecting means, connected to said delayed signal generating means, for detecting a position of said delayed signal from one of a plurality of said delay elements at a time when the second signal is input thereto; counting means, connected to said delayed signal generating means, for counting a number of times that said delayed signal travels between said end and beginning delay elements; and detecting means, connected to said position detecting means and to said counting means, for detecting a phase difference between said first and second signals using a count from said counting means and a detected position of said delayed signal detected by said position detecting means.

Claim 3

A phase difference detecting circuit according to claim 1, wherein said first and second signals are pulse signals.

Claim 4

A time difference detecting means for providing a signal indicating a time difference between a first signal and a second signal, comprising: a delayed pulse generating means having a plurality of delay elements connected in series to form a series circuit, receiving said first signal, for generating a plurality of delayed pulses while said first signal is passing through the delay elements; a detecting means, connected to said delayed pulse generating means and receiving said delayed pulses, for detecting a latest one of said delayed pulses when receiving said second signal a certain time after said first signal and generating a detecting signal indicating a time period elapsed between the time when said first signal is input thereto and the time when said second signal is input thereto; means, connected to said delayed pulse generating means, for connecting one end of the series circuit to an other end thereof to repeatedly circulate said delayed pulses from the one end toward the other end through the delay elements of the series circuit; counting means, connected to said delayed pulse generating means, for counting a number of times that the delayed pulses circulate in the series circuit; and means, connected to said detecting means and to said counting means, for combining the detecting signal from the detecting means with the number of times of circulation counted by the counting means, to indicate a time difference between the first and second signals.

Claim 5

A time difference detecting means for providing a signal indicating a time difference between a first signal and a second signal, comprising: a delayed pulse generating means having a plurality of delay elements connected in series to form a series circuit, receiving said first signal, for generating a plurality of delayed pulses while said first signal is passing through the delay elements; a detecting means, connected to said delayed pulse generating means and receiving said delayed pulses, for detecting a latest one of said delayed pulses when receiving said second signal a certain time after said first signal and generating a detecting signal indicating a time period elapsed between the time when said first signal is input thereto and the time when said second signal is input thereto; means, connected to said delayed pulse generating means, for connecting one end of the series circuit to an other end thereof to repeatedly circulate said delayed pulses from the one end toward the other end through the delay elements of the series circuit; counting means, connected to said delayed pulse generating means, for counting a number of times that the delayed pulses circulate in the series circuit; and means, connected to said detecting means and to said counting means, for combining the detecting signal from the detecting means with the number of times of circulation counted by the counting means, to indicate a time difference between the first and second signals.

Claim 6

A time difference detecting means according to claim 3, wherein said counting means comprises a first counter and a second counter, and said first counter connected to a first output point in said delay pulse generating means for receiving a count signal whenever said first signal passes through the first output point, counting the first number of rounds of circulation of said first signal, and providing a result of the counting; said second counter connected to a second output point located in said delay pulse generating means for receiving a count signal whenever said first signal passes through the second output point, counting the number of rounds of circulation of said first signal, and providing a result of the counting; and wherein, when both of the counted numbers of said two counters are identical, either one of said counted numbers is output while when the counted numbers of both counters are different from each other, the one of said counted numbers having a smaller number than that of the other is output.

Claim 7

A time difference detecting means according to claim 3, wherein said counter outputs its counted number when said second signal is input thereto.

Claim 8

A time difference detecting means according to claim 3, wherein the number of said delay pulse generating means comprises an odd number of delay elements.

Claim 9

A time difference detecting means according to claim 3, wherein the number of said delay elements of said delay pulse generating means is other than 2 n (n being a positive integer), and the detecting signal whose upper bits are formed from an output of the counting means and whose lower bits are formed from an output of the detecting means is processed through a predetermined operation, thereby providing a continuous digital signal indicating a time difference between the first and second signals.

Claim 10

A phase difference detecting circuit for detecting a phase difference between a first signal and a second signal subsequent to said first signal, said circuit comprising: a series circuit including a plurality of serially-connected delay elements having an end delay element connected to a beginning delay element to form a ring circuit, said first signal being input to any one connecting portion formed between any two delay elements, a delayed signal being produced at each said connecting portion of each said delay element which is sequentially delayed from one connecting portion to another; an encoder, connected to said series circuit and to receive said second signal to detect a position of said delayed signal from one of a plurality of said delay elements, at a time when the second signal is input thereto; a counter circuit, connected to said series circuit to count a number of times that said delayed signal travels between said end and beginning delay elements; and detecting means for detecting a phase difference between said first and second signals using a count from said counter circuit and a detected position of said delayed signal detected by said encoder.

Claim 11

A phase difference detecting circuit for detecting a phase difference between a first signal and a second signal subsequent to said first signal, said circuit comprising: a series circuit including a plurality of serially-connected delay elements having an end delay element connected to a beginning delay element to form a ring circuit, said first signal being input to any one connecting portion formed between any two delay elements, a delayed signal being produced at each said connecting portion of each said delay element which is sequentially delayed from one connecting portion to another; an encoder, connected to said series circuit and to receive said second signal to detect a position of said delayed signal from one of a plurality of said delay elements, at a time when the second signal is input thereto; a counter circuit, connected to said series circuit to count a number of times that said delayed signal travels between said end and beginning delay elements; and detecting means for detecting a phase difference between said first and second signals using a count from said counter circuit and a detected position of said delayed signal detected by said encoder.

Claim 12

A phase difference detecting circuit according to claim 8, wherein said first and second signals are pulse signals.

Claim 13

A time difference detector for providing a signal indicating a time difference between a first signal and a second signal, comprising: a plurality of delay elements connected in series to form a series circuit, receiving said first signal, and generating a plurality of delayed pulses while said first signal is passing through the delay elements; an encoder circuit connected to said series circuit to receive said delayed pulses, configured to detect a latest one of said delayed pulses when receiving said second signal a certain time after said first signal, and generating a detecting signal indicating a time between an input of said first signal and an input of said second signal; a connecting element connected between one end of the series circuit and an other end thereof, to repeatedly circulate said delayed pulses from the one end toward the other end through the delay elements of the series circuit; a counter circuit connected to count a number of times that the delayed pulses circulate in the connecting element of the series circuit; and means for combining the detecting signal from the encoder with the number of times of circulation counted by the counter, to indicate a time difference between the first and second signals.

Claim 14

A time difference detector for providing a signal indicating a time difference between a first signal and a second signal, comprising: a plurality of delay elements connected in series to form a series circuit, receiving said first signal, and generating a plurality of delayed pulses while said first signal is passing through the delay elements; an encoder circuit connected to said series circuit to receive said delayed pulses, configured to detect a latest one of said delayed pulses when receiving said second signal a certain time after said first signal, and generating a detecting signal indicating a time between an input of said first signal and an input of said second signal; a connecting element connected between one end of the series circuit and an other end thereof, to repeatedly circulate said delayed pulses from the one end toward the other end through the delay elements of the series circuit; a counter circuit connected to count a number of times that the delayed pulses circulate in the connecting element of the series circuit; and means for combining the detecting signal from the encoder with the number of times of circulation counted by the counter, to indicate a time difference between the first and second signals.

Claim 15

A time difference detector according to claim 10, wherein said counter circuit comprises a first counter and a second counter, and said first counter connected to a first output point in said series circuit for receiving a count signal whenever said first signal passes through the first output point, counting the first number of rounds of circulation of said first signal, and providing a result of the counting; said second counter connected to a second output point located in said series circuit for receiving a count signal whenever said first signal passes through the second output point, counting the number of rounds of circulation of said first signal, and providing a result of the counting; and wherein, when both of the counted numbers of said two counters are identical, either one of said counted numbers is output while when the counted numbers of both counters are different from each other, the one of said counted numbers having a smaller number than that of the other is output.

Claim 16

A time difference detector according to claim 10, wherein said counter outputs its counted number when said second signal is input thereto.

Claim 17

A time difference detector according to claim 10, wherein there are an odd number of delay elements.

Claim 18

A time difference detector according to claim 10, wherein the number of said delay elements of said series circuit is other than 2 n (n being a positive integer), and the detecting signal whose upper bits are formed from an output of the counter and whose lower bits are formed from an output of the encoder is processed through a predetermined operation, thereby providing a continuous digital signal indicating a time difference between the first and second signals.