Phase modulator of two dynamic counters

Claim 2

In combination: first and second counters, each having an equal number of counting stages; a pulse source coupled to said counters for applying a train of pulses thereto in parallel; phase detection means for providing in succession a plurality of different resolutions of in-phase operation of said counters from a coarse to a fine resolution and for producing a first control signal indicating an out-of-phase condition until an in-phase operation is reached within said fine resolution; lead-lag detection means for providing an indication of the relative phase of said second counter signal indicating the lead-lag condition of said second counter to said first counter; and modulation means response to said second control signal for modulating the pulses applied to said first counter from said pulse source to reduce the relative phase difference between said counters until said first control signal no longer indicates an out-of-phase condition.

Claim 3

The invention in accordance with claim 1, wherein the resolution capability of the finest resolution is within one pulse cycle period of pulses from said source.

Claim 4

The invention in accordance with claim 2, wherein said modulation means provides for modulation of the pulses applied to said first counter from said source by interjecting additional pulses in said pulse train in order to advance the phase of said first counter and interrupting pulses in said pulse train in order to retard the phase of said first counter.

Claim 5

The invention according to claim 1 wherein said phase detection means provides for each of said different resolutions of in-phase operation of said counters a means for comparing the phases of corresponding stages selected for a given resolution having equal output signal frequencies greater than corresponding stages selected for resOlutions which are more coarse than said given resolution, and wherein said lead-lag detection means provides the relative phase of said second counter to said first counter based upon the relative phase of output signals from corresponding stages selected for the most coarse of said plurality of resolutions.

Claim 6

The invention according to claim 4 wherein said phase comparing means for a given resolution provides an out-of-phase indication until an out-of-phase indication is no longer present in a phase comparing means for a more coarse resolution, and said phase comparing means for the finest resolution produces said first control signal until both an out-of-phase indication is no longer present in the phase comparing means of the next finest resolution and an out-of-phase indication is no longer present in said comparing means for the finest resolution.

Claim 7

The invention according to claim 1 wherein said phase detection means provides for each of said plurality of different resolutions comparing the phase of a signal derived from a stage of said first counter with a signal derived from a corresponding stage of said second counter at a time determined by a synchronized signal at a higher frequency; and wherein said lead-lag detection means provides the relative phase of said second counter with respect to said first counter based upon the relative phases of output signals from corresponding stages selected for comparison in the most coarse of said plurality of resolutions.

Claim 8

The invention according to claim 6 wherein said phase comparing means for a given resolution is adapted to provide an out-of-phase indication until an out-of-phase indication is no longer present in a phase comparing means for a more coarse resolution, and said phase comparing means for the finest resolution produces said first control signal until both an out-of-phase indication is no longer present in the phase comparing means of the next finest resolution and an out-of-phase indication is no longer present in said comparing means for the finest resolution.

Claim 9

The invention according to claim 7 wherein said comparing means for the finest resolution comprises: means for forming the logic function f0.C1.C2, where fo represents the train of pulses from said pulse source, C1 represents one of said signals being compared and C2 represents the binary complement of the other one of said signals being compared; bistable storage means; means responsive to said function f0.C1.C2 at the end of each period of one of said signals being compared for setting and storage means when said function is true and for resetting said storage means when said function is false, thereby producing said first control signal while said storage means is set; and means for holding said storage means set until said comparing means for the next lower resolution is no longer indicating an out-of-phase condition.

Claim 10

The invention according to claim 8 wherein said comparing means for each resolution more coarse than the finest resolution comprises: means for forming the logic function fn.Cln.C2n where fn represents a signal at a higher frequency than signals being compared of corresponding stages of said first and second counter, C1n represents one of said signals being compared and C2n represents the binary complement of the other one of said signals being compared; bistable storage means; and means responsive to said function fn.Cln.C2n at the end of each period of one of said signals being compared for setting said storage means when said function is true and resetting said storage means when said function is false, thereby indicating an out-of-phase condition; and wherein said comparing means for each resolution more coarse than the finest resolutioN, except the most coarse resolution, includes means for holding said storage means thereof set until said comparing means for the next lower resolution is no longer indicating an out-of-phase condition.