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US5289119A
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US
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Transparent enable test circuit
Assignee: Unisys Corp
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Filing: 1992-04-20
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Granted: 1994-02-22
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Expires: 2012-04-20
Abstract
Abstract A test circuit for two level latches on an integrated circuit to be tested includes a test enable driver circuit coupled to a third level switch which is connected in series between the latches to be tested and a low voltage source. The third level switch converts the two level latches to be tested into a buffer such that data applied as an input to the two level latches appears in identical form as data at the output pin of the integrated circuit chip.
Inventors
- 👤 Duane A. Schroeder
- 👤 David M. Hime
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 22:54
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318544; G01R31/318547; G01R31/318522; G01R31/318525; G01R31/318541
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
172 words
A transparent enable mode test circuit for testing two level switch devices, comprising: an integrated circuit chip device comprising a plurality of two level transistorized switches, having first and second levels to be tested, each of said switches to be tested having a data input line for latching data therein, each of said switches to be tested being coupled to an output pin on said chip for detecting the state condition of said two level switches, transparent enable switch means coupled between said second level of said two level transistorized switches to be tested and a voltage current source for said two level switches, said transparent enable switch means having input transistor means and reference transistor means, a test enable circuit having an output coupled to the input of said input transistor means of said transparent enable switch means, whereby a first level enable test signal applied to said test enable circuit maintains said two level switch in its fixed state and it is enabled to be operable in a transparent mode.
Claim 2
Dependent Claim
172 words
A transparent enable mode test circuit for testing two level switch devices, comprising: an integrated circuit chip device comprising a plurality of two level transistorized switches, having first and second levels to be tested, each of said switches to be tested having a data input line for latching data therein, each of said switches to be tested being coupled to an output pin on said chip for detecting the state condition of said two level switches, transparent enable switch means coupled between said second level of said two level transistorized switches to be tested and a voltage current source for said two level switches, said transparent enable switch means having input transistor means and reference transistor means, a test enable circuit having an output coupled to the input of said input transistor means of said transparent enable switch means, whereby a first level enable test signal applied to said test enable circuit maintains said two level switch in its fixed state and it is enabled to be operable in a transparent mode.
Claim 3
Dependent Claim
29 words
A test circuit as set forth in claim 1 wherein one of said plurality of said two level transistor switches to be tested comprises a conventional transistorized latch circuit.
Claim 4
Dependent Claim
72 words
A test circuit as set forth in claim 2 wherein said one of said plurality of said two level transistorized switches to be tested comprises a master latch, a slave latch coupled to said master latch to form a convention flip-flop therewith, and said transparent enable switch means comprises a pair of third level switches coupled between said second level of said two level switches of said master and said slave latches.
Claim 5
Dependent Claim
61 words
A test circuit as set forth in claim 2 wherein said conventional transistorized latch circuit comprises an input pair of ECL transistors and an output pair of ECL transistors, and an emitter follower driver transistor coupled to each of the outputs of aid output pair of said ECL transistors providing a high and a low slave latch output from said chip.
Claim 6
Dependent Claim
79 words
A test circuit as set forth in claim 4 wherein said plurality of two level transistorized switches each comprises a two level flip-flop, each of said flip-flops comprises a master and a slave two level latch, and each of said two level latches is coupled to a voltage source through one of a pair of third level switches, said one of a pair of third level switches comprising said transparent enable switch means coupled to said test enable circuit.
Claim 7
Dependent Claim
23 words
A test circuit a set forth in claim 5 which further includes output driver means coupled to said slave latch of said flip-flop.
Claim 8
Dependent Claim
47 words
A test circuit test as set forth in claim 6 wherein said test enable circuit has an output coupled to the inputs of said input transistor means of said transparent enable switch means which comprises the input transistor of each said pair of said third level switches.
Claim 9
Independent Claim
150 words
A method of testing two level transistorized switch device of the type having first and second levels and a voltage current source on a integrated circuit ship, comprising the steps of: connecting a third level switch device between the second level of the switch device to be tested and its voltage current source, providing a test enable circuit at the input of said chip, coupling the output of said test enable circuit to said input of said third level switch device, applying a first level signal to said test enable circuit so that said two level switch device is placed in a high state, whereby said two level switch device is placed in a high state, whereby said two level switch device is placed in a transparent mode so that said two level switch device passes data applied to its input directly to the output of said two level device.
Claim 10
Independent Claim
150 words
A method of testing two level transistorized switch device of the type having first and second levels and a voltage current source on a integrated circuit ship, comprising the steps of: connecting a third level switch device between the second level of the switch device to be tested and its voltage current source, providing a test enable circuit at the input of said chip, coupling the output of said test enable circuit to said input of said third level switch device, applying a first level signal to said test enable circuit so that said two level switch device is placed in a high state, whereby said two level switch device is placed in a high state, whereby said two level switch device is placed in a transparent mode so that said two level switch device passes data applied to its input directly to the output of said two level device.
Claim 11
Dependent Claim
68 words
A method of testing two level transistorized switch device as set forth in claim 8 which further includes the steps of: applying a second level signal to said test enable circuit to switch said two level switch device to a reset or low state where said data and a clock applied to said two level switch device will set said two level switch device in an operable mode.
Claim 12
Dependent Claim
84 words
A method of testing two level transistorized switch device as set forth in claim 8 wherein said second level of said two level switch device comprises a latch circuit means having a first level input transistor having its base coupled to a data input source, and said step of applying said first level signal to said test enable circuit comprises setting said first level input transistor into a conducting state so that data passes through said two level switch device in a transparent mode.
Claim 13
Dependent Claim
33 words
A method of testing as set forth in claim 10 which further comprises the steps of: applying a test pattern to said data input source coupled to the base of said input transistor.
Claim 14
Dependent Claim
28 words
A method of testing as set forth in claim 11 which further includes the steps of: recording said test pattern at the output of said latch circuit means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-02-21 | 1997-08-23 | 1998-02-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-02-21 | 2001-08-23 | 2002-02-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-02-21 | 2005-08-23 | 2006-02-22 | $7700.00 | Window Closed / Lapsed |