Fast electronic comparator

Claim 2

A semiconductor circuit comprising: inverter with an input and an output, said inverter being responsive to the voltage at said input of said inverter such that when said voltage at said input of said inverter is greater than a balance-point voltage the output of said inverter switches to a first state, said inverter being responsive to said voltage at said input of said inverter such that when said voltage at said input of said inverter is less than said balance-point voltage said output of said inverter switches to a second state; first transistor of a first conductivity type, the gate of said first transistor being coupled to the drain of said first transistor, the drain of said first transistor being coupled to said input of said inverter, the source of said first transistor being coupled to the power supply voltage; second transistor of a second conductivity type, the gate of said second transistor being coupled to the drain of said second transistor, the drain of said second transistor being coupled to said input of said inverter, the source of said second transistor being coupled to ground; and said first transistor and said second transistor being the same sizes as the transistors of the same conductivity type in said inverter such that said balance-point voltage of said inverter is established at the input of said inverter.

Claim 3

The circuit of claim 1 wherein said first conductivity type is P-type and said second conductivity type is N-type.

Claim 4

In a semiconductor circuit having an inverter with an input and an output, said inverter being responsive to the voltage at said input of said inverter such that when said voltage at said input of said inverter is greater than a balance-point voltage the output of said inverter switches to a first state, said inverter being responsive to said voltage at said input of said inverter such that when said voltage at said input of said inverter is less than said balance-point voltage said output of said inverter switches to a second state, the improvement comprising: negative feedback circuit for receiving said output of said inverter and generating a negative feedback signal coupled to said input of said inverter, said negative feedback signal preventing said voltage at said input of said inverter from increasing above a first predetermined voltage above said balance-point voltage when said output of said inverter is in said first state, said feedback signal preventing said voltage at said input of said inverter from decreasing below a second predetermined voltage below said balance-point voltage when said output of said inverter is in said second state wherein said first predetermined voltage is less than a positive power supply voltage wherein said second predetermined voltage is greater than ground potential.

Claim 5

In a semiconductor circuit having an inverter with an input and an output, said inverter being responsive to the voltage at said input of said inverter such that when said voltage at said input of said inverter is greater than a balance-point voltage the output of said inverter switches to a first state, said inverter being responsive to said voltage at said input of said inverter such that when said voltage at said input of said inverter is less than said balance-point voltage said output of said inverter switches to a second state, the improvement comprising: negative feedback circuit for receiving said output of said inverter and generating a negative feedback signal coupled to said input of said inverter, said negative feedback signal preventing said voltage at said input of said inverter from increasing above a first predetermined voltage above said balance-point voltage when said output of said inverter is in said first state, said feedback signal preventing said voltage at said input of said inverter from decreasing below a second predetermined voltage below said balance-point voltage when said output of said inverter is in said second state wherein said first predetermined voltage is less than a positive power supply voltage wherein said second predetermined voltage is greater than ground potential.

Claim 6

In a semiconductor circuit having an inverter with an input and an output, said inverter being responsive to the voltage at said input of said inverter such that when said voltage at said input of said inverter is greater than a balance-point voltage the output of said inverter switches to a first state, said inverter being responsive to said voltage at said input of said inverter such that when said voltage at said input of said inverter is less than said balance-point voltage said output of said inverter switches to a second state, the improvement comprising: first transistor of a first conductivity type, the gate of said first transistor being coupled to said output of said inverter, the source of said first transistor being coupled to said input of said inverter, the drain of said first transistor being coupled to the power supply voltage; second transistor of a second conductivity type, the gate of said second transistor being coupled to said output of said inverter, the gate of said second transistor being coupled to said gate of said first transistor, the source of said second transistor being coupled to said input of said inverter, the drain of said second transistor being coupled to ground.

Claim 7

In a semiconductor circuit having an inverter with an input and an output, said inverter being responsive to the voltage at said input of said inverter such that when said voltage at said input of said inverter is greater than a balance-point voltage the output of said inverter switches to a first state, said inverter being responsive to said voltage at said input of said inverter such that when said voltage at said input of said inverter is less than said balance-point voltage said output of said inverter switches to a second state, the improvement comprising: first transistor of a first conductivity type, the gate of said first transistor being coupled to said output of said inverter, the source of said first transistor being coupled to said input of said inverter, the drain of said first transistor being coupled to the power supply voltage; second transistor of a second conductivity type, the gate of said second transistor being coupled to said output of said inverter, the gate of said second transistor being coupled to said gate of said first transistor, the source of said second transistor being coupled to said input of said inverter, the drain of said second transistor being coupled to ground.

Claim 8

The circuit of claim 4 wherein said first conductivity type is P-type and said second conductivity type is N-type.

Claim 9

An integrated circuit for comparing a first input signal to a second input signal and generating an output signal corresponding to the voltage difference between said first input signal and said second input signal comprising: first current source means for generating a first current; differential pair means for receiving said first input signal, said second input signal, and said first current and generating a second current at a second output node and a third current at a third output node, said second current and said third current each being proportional to the voltage difference between said first input signal and said second input signal; second current source means for generating a fourth current; current-mirror means for receiving said second current and said fourth current and generating a fifth current, said fifth current being substantially equal to the sum of said second current and said fourth current, said current-mirror being coupled to said third output node such that said fifth current is directed away from said third output node, said fourth current preventing said current-mirror from turning off when said second current is zero; fourth current source means for generating a sixth current; fifth current source means for generating a seventh current; folded-cascode means for receiving said sixth current and said seventh current at a folded-cascode input and generating an eighth current at a folded-cascode output, said folded-cascode means also having a bidirectional input for allowing current to flow between said folded-cascode input and said bidirectional input, said bidirectional input being coupled to said third output node, said eighth current being substantially equal to said sixth current and said seventh current being substantially equal to said fourth current such that the current flowing between said folded-cascode input and said bidirectional input is substantially determined by the difference between said second current and said third current, said folded-cascode providing impedance buffering from said bidirectional input to said folded-cascode input, said folded-cascode input being at a balance-point voltage when said first input signal and said second input signal are substantially equal; first inverter means for receiving said folded-cascode input and generating a first voltage, said folded-cascode input being coupled to the input of said first inverter means; voltage clamping means coupled to said input of said first inverter means for substantially clamping said voltage at said input to said inverter at said balance-point voltage, said voltage clamping means allowing said voltage at said input of said inverter to only slightly increase above said balance-point voltage, said clamping means allowing said voltage at said input of said inverter to only slightly decrease below said balance-point voltage; capacitor means coupled to said folded-cascode input and said second voltage for capacitively coupling said folded-cascode input and said second voltage; and third inverter means for receiving said second voltage and generating said output signal.

Claim 10

An integrated circuit for comparing a first input signal to a second input signal and generating an output signal corresponding to the voltage difference between said first input signal and said second input signal comprising: first current source means for generating a first current; differential pair means for receiving said first input signal, said second input signal, and said first current and generating a second current at a second output node and a third current at a third output node, said second current and said third current each being proportional to the voltage difference between said first input signal and said second input signal; second current source means for generating a fourth current; current-mirror means for receiving said second current and said fourth current and generating a fifth current, said fifth current being substantially equal to the sum of said second current and said fourth current, said current-mirror being coupled to said third output node such that said fifth current is directed away from said third output node, said fourth current preventing said current-mirror from turning off when said second current is zero; fourth current source means for generating a sixth current; fifth current source means for generating a seventh current; folded-cascode means for receiving said sixth current and said seventh current at a folded-cascode input and generating an eighth current at a folded-cascode output, said folded-cascode means also having a bidirectional input for allowing current to flow between said folded-cascode input and said bidirectional input, said bidirectional input being coupled to said third output node, said eighth current being substantially equal to said sixth current and said seventh current being substantially equal to said fourth current such that the current flowing between said folded-cascode input and said bidirectional input is substantially determined by the difference between said second current and said third current, said folded-cascode providing impedance buffering from said bidirectional input to said folded-cascode input, said folded-cascode input being at a balance-point voltage when said first input signal and said second input signal are substantially equal; first inverter means for receiving said folded-cascode input and generating a first voltage, said folded-cascode input being coupled to the input of said first inverter means; voltage clamping means coupled to said input of said first inverter means for substantially clamping said voltage at said input to said inverter at said balance-point voltage, said voltage clamping means allowing said voltage at said input of said inverter to only slightly increase above said balance-point voltage, said clamping means allowing said voltage at said input of said inverter to only slightly decrease below said balance-point voltage; capacitor means coupled to said folded-cascode input and said second voltage for capacitively coupling said folded-cascode input and said second voltage; and third inverter means for receiving said second voltage and generating said output signal.

Claim 11

An integrated circuit for comparing a first input signal to a second input signal and generating an output signal corresponding to the voltage difference between said first input signal and said second input signal comprising: first current source means for generating a first current; differential pair means for receiving said first input signal, said second input signal, and said first current and generating a second current at a second output node and a third current at a third output node, said second current and said third current each being proportional to the voltage difference between said first input signal and said second input signal; second current source means for generating a fourth current; current-mirror means for receiving said second current and said fourth current and generating a fifth current, said fifth current being substantially equal to the sum of said second current and said fourth current, said current-mirror being coupled to said third output node such that said fifth current is directed away from said third output node, said fourth current preventing said current-mirror from turning off when said second current is zero; fourth current source means for generating a sixth current; fifth current source means for generating a seventh current; folded-cascode means for receiving said sixth current and said seventh current at a folded-cascode input and generating an eighth current at a folded-cascode output, said folded-cascode means also having a bidirectional input for allowing current to flow between said folded-cascode input and said bidirectional input, said bidirectional input being coupled to said third output node, said eighth current being substantially equal to said sixth current and said seventh current being substantially equal to said fourth current such that the current flowing between said folded-cascode input and said bidirectional input is substantially determined by the difference between said second current and said third current, said folded-cascode providing impedance buffering from said bidirectional input to said folded-cascode input, said folded-cascode input being at a balance-point voltage when said first input signal and said second input signal are substantially equal; first inverter for receiving said folded-cascode input and generating a first voltage; negative feedback circuit for receiving said first voltage and generating a negative feedback signal coupled to said input of said inverter, said negative feedback signal allowing said voltage at said input of said inverter to only slightly increase above said balance-point voltage when said output of said inverter is in a first state, said feedback signal allowing said voltage at said input of said inverter to only slightly decrease below said balance-point voltage when said output of said inverter is in a second state; capacitor means coupled to said folded-cascode input and said second voltage for capacitively coupling said folded-cascode input and said second voltage; and third inverter means for receiving said second voltage and generating said output signal.

Claim 12

An integrated circuit for comparing a first input signal to a second input signal and generating an output signal corresponding to the voltage difference between said first input signal and said second input signal comprising: first current source means for generating a first current; differential pair means for receiving said first input signal, said second input signal, and said first current and generating a second current at a second output node and a third current at a third output node, said second current and said third current each being proportional to the voltage difference between said first input signal and said second input signal; second current source means for generating a fourth current; current-mirror means for receiving said second current and said fourth current and generating a fifth current, said fifth current being substantially equal to the sum of said second current and said fourth current, said current-mirror being coupled to said third output node such that said fifth current is directed away from said third output node, said fourth current preventing said current-mirror from turning off when said second current is zero; fourth current source means for generating a sixth current; fifth current source means for generating a seventh current; folded-cascode means for receiving said sixth current and said seventh current at a folded-cascode input and generating an eighth current at a folded-cascode output, said folded-cascode means also having a bidirectional input for allowing current to flow between said folded-cascode input and said bidirectional input, said bidirectional input being coupled to said third output node, said eighth current being substantially equal to said sixth current and said seventh current being substantially equal to said fourth current such that the current flowing between said folded-cascode input and said bidirectional input is substantially determined by the difference between said second current and said third current, said folded-cascode providing impedance buffering from said bidirectional input to said folded-cascode input, said folded-cascode input being at a balance-point voltage when said first input signal and said second input signal are substantially equal; first inverter for receiving said folded-cascode input and generating a first voltage; negative feedback circuit for receiving said first voltage and generating a negative feedback signal coupled to said input of said inverter, said negative feedback signal allowing said voltage at said input of said inverter to only slightly increase above said balance-point voltage when said output of said inverter is in a first state, said feedback signal allowing said voltage at said input of said inverter to only slightly decrease below said balance-point voltage when said output of said inverter is in a second state; capacitor means coupled to said folded-cascode input and said second voltage for capacitively coupling said folded-cascode input and said second voltage; and third inverter means for receiving said second voltage and generating said output signal.