IEEE 488 interface for message handling method

Claim 2

A bus interface which couples a microprocessor to an IEEE 488 bus, the interface comprising: a microprocessor port which transmits and receives data to and from said microprocessor; said microprocessor port including microprocessor data bus lines and a write line for receiving write pulses from said microprocessor; each said write pulses having a predefined duration and a trailing edge; an IEEE 488 bus; said IEEE 488 bus including data lines and a data valid (DAV) line; talker circuit means, coupled to said microprocessor port and said IEEE 488 bus, for asserting data received by said microprocessor port onto said IEEE 488 bus; said talker circuit means including a transparent latch for asserting and latching data received from said microprocessor port onto said IEEE 488 bus such that data received from said microprocessor port is asserted onto said IEEE 488 bus before the trailing edge of said write pulses; and source handshake means, coupled to said talker circuit means and said IEEE 488 bus, for asserting a signal on said DAV line of said IEEE 488 bus after said talker circuit has asserted data on said IEEE 488 bus for a first predefined minimum settling period; said source handshake means including speedup means that, when enabled, asserts said signal on said DAV line of said IEEE 488 bus after said talker circuit has asserted data on said IEEE 488 bus for a second predefined settling period that is less than said first predefined minimum settling period; whereby speed of transmission of data by said microprocessor is improved by reducing said settling period.

Claim 3

The interface set forth in claim 1, said interface including a speedup enable switch for enabling said speedup means.

Claim 4

A bus interface that couples a microprocessor having a direct memory access controller to an IEEE 488 bus, the interface comprising: a microprocessor port that transmits and receives data to and from said microprocessor; said microprocessor having an interrupt signal port; said microprocessor port including at least one line for transmitting interrupt signals to said interrupt signal port of said microprocessor; an IEEE 488 bus; said IEEE 488 bus including data lines and a data valid (DAV) line; listener circuit means, coupled to said microprocessor port and said IEEE 488 bus, for transmitting data from said IEEE 488 bus to said microprocessor via said microprocessor port; and acceptor handshake means, coupled to said listener circuit means and said IEEE 488 bus, for detecting when the last byte of a data transfer has been received from said IEEE 488 bus while said listener circuit means is transmitting data to said microprocessor via said microprocessor port and for then transmitting a first interrupt signal to said interrupt signal port of said microprocessor via said microprocessor port; and synchronization means, coupled to said IEEE 488 bus, for detecting when a data valid signal previously asserted on said DAV line is unasserted, and for then transmitting a second interrupt signal to said interrupt signal port of said microprocessor via said microprocessor port; and a synchronization interrupt enable switch for enabling said synchronization means to send said second interrupt signal to said microprocessor; wherein said synchronization means does not send said second interrupt signal when a data valid signal previously asserted on said DAV line is unasserted unless said synchronization interrupt enable switch is enabled; said synchronization interrupt enable switch coupled to said microprocessor via said microprocessor port so that said microprocessor can enable and disable said synchronization interrupt enable switch; whereby said microprocessor is automatically notified by said first interrupt signal that the last byte of a data transfer has been transmitted by said interface from said IEEE 488 bus to said microprocessor and said microprocessor is automatically notified by said second interrupt signal that said IEEE 488 bus has completed the data transfer; wherein said microprocessor port includes a write line for receiving write pulses from said microprocessor; each said write pulses having a predefined duration and a trailing edge; said interface further including: talker circuit means, coupled to said microprocessor port and said IEEE 488 bus, for asserting data received by said microprocessor port onto said IEEE 488 bus; said talker circuit means including a transparent latch for asserting and latching data received from said microprocessor port onto said IEEE 488 bus such that data received from said microprocessor port is asserted onto said IEEE 488 bus before the trailing edge of said write pulses; and source handshake means, coupled to said talker circuit means and said IEEE 488 bus, for asserting a signal on said DAV line of said IEEE 488 bus after said talker circuit has asserted data on said IEEE 488 bus for a first predefined minimum settling period; said source handshake means including speedup means that, when enabled, asserts said signal on said DAV line of said IEEE 488 bus after said talker circuit has asserted data on said IEEE 488 bus for a second predefined settling period that is less than said first predefined minimum settling period; whereby speed of transmission of data by said microprocessor is improved by reducing said settling period.

Claim 5

A bus interface that couples a microprocessor having a direct memory access controller to an IEEE 488 bus, the interface comprising: a microprocessor port that transmits and receives data to and from said microprocessor; said microprocessor having an interrupt signal port; said microprocessor port including at least one line for transmitting interrupt signals to said interrupt signal port of said microprocessor; an IEEE 488 bus; said IEEE 488 bus including data lines and a data valid (DAV) line; listener circuit means, coupled to said microprocessor port and said IEEE 488 bus, for transmitting data from said IEEE 488 bus to said microprocessor via said microprocessor port; and acceptor handshake means, coupled to said listener circuit means and said IEEE 488 bus, for detecting when the last byte of a data transfer has been received from said IEEE 488 bus while said listener circuit means is transmitting data to said microprocessor via said microprocessor port and for then transmitting a first interrupt signal to said interrupt signal port of said microprocessor via said microprocessor port; and synchronization means, coupled to said IEEE 488 bus, for detecting when a data valid signal previously asserted on said DAV line is unasserted, and for then transmitting a second interrupt signal to said interrupt signal port of said microprocessor via said microprocessor port; and a synchronization interrupt enable switch for enabling said synchronization means to send said second interrupt signal to said microprocessor; wherein said synchronization means does not send said second interrupt signal when a data valid signal previously asserted on said DAV line is unasserted unless said synchronization interrupt enable switch is enabled; said synchronization interrupt enable switch coupled to said microprocessor via said microprocessor port so that said microprocessor can enable and disable said synchronization interrupt enable switch; whereby said microprocessor is automatically notified by said first interrupt signal that the last byte of a data transfer has been transmitted by said interface from said IEEE 488 bus to said microprocessor and said microprocessor is automatically notified by said second interrupt signal that said IEEE 488 bus has completed the data transfer; wherein said microprocessor port includes a write line for receiving write pulses from said microprocessor; each said write pulses having a predefined duration and a trailing edge; said interface further including: talker circuit means, coupled to said microprocessor port and said IEEE 488 bus, for asserting data received by said microprocessor port onto said IEEE 488 bus; said talker circuit means including a transparent latch for asserting and latching data received from said microprocessor port onto said IEEE 488 bus such that data received from said microprocessor port is asserted onto said IEEE 488 bus before the trailing edge of said write pulses; and source handshake means, coupled to said talker circuit means and said IEEE 488 bus, for asserting a signal on said DAV line of said IEEE 488 bus after said talker circuit has asserted data on said IEEE 488 bus for a first predefined minimum settling period; said source handshake means including speedup means that, when enabled, asserts said signal on said DAV line of said IEEE 488 bus after said talker circuit has asserted data on said IEEE 488 bus for a second predefined settling period that is less than said first predefined minimum settling period; whereby speed of transmission of data by said microprocessor is improved by reducing said settling period.

Claim 6

The interface set forth in claim 3, said interface including speedup enable switch for enabling said speedup means.

Claim 7

A bus interface which couples a microprocessor having a direct memory access controller to an IEEE 488 bus, the interface comprising: a microprocessor port which transmits and receives data to and from said microprocessor having a direct memory access controller which generates a terminal count (TC) signal upon transmission of any specified datum in a multiple datum data transfer; said microprocessor port including microprocessor data bus lines and a terminal count line for receiving said TC signals from said direct memory access controller; an IEEE 488 bus; said IEEE 488 bus including data lines and a NOT READY FOR DATA (NRFD) line; listener circuit means, coupled to said microprocessor port and said IEEE 488 bus, for transmitting data from said IEEE 488 bus to said microprocessor via said microprocessor port; and acceptor handshake means, coupled to said listener circuit means and said IEEE 488 bus, for asserting a holdoff signal on said NRFD line of said IEEE 488 bus when said microprocessor port receives a TC signal from said direct memory access controller until a predefined condition is met; whereby said acceptor handshake means automatically performs a data holdoff upon transmission of any specified datum in a multiple datum DMA data transfer from said IEEE 488 bus to said microprocessor.

Claim 8

A bus interface which couples a microprocessor having a direct memory access controller to an IEEE 488 bus, the interface comprising: a microprocessor port which transmits and receives data to and from said microprocessor having a direct memory access controller which generates a terminal count (TC) signal upon transmission of any specified datum in a multiple datum data transfer; said microprocessor port including microprocessor data bus lines and a terminal count line for receiving said TC signals from said direct memory access controller; an IEEE 488 bus; said IEEE 488 bus including data lines and a NOT READY FOR DATA (NRFD) line; listener circuit means, coupled to said microprocessor port and said IEEE 488 bus, for transmitting data from said IEEE 488 bus to said microprocessor via said microprocessor port; and acceptor handshake means, coupled to said listener circuit means and said IEEE 488 bus, for asserting a holdoff signal on said NRFD line of said IEEE 488 bus when said microprocessor port receives a TC signal from said direct memory access controller until a predefined condition is met; whereby said acceptor handshake means automatically performs a data holdoff upon transmission of any specified datum in a multiple datum DMA data transfer from said IEEE 488 bus to said microprocessor.

Claim 9

The interface set forth in claim 5, wherein said microprocessor port includes a write line for receiving write pulses from said microprocessor; each said write pulses having a predefined duration and a trailing edge; said IEEE 488 bus including a data valid (DAV) line; said interface further including: talker circuit means, coupled to said microprocessor port and said IEEE 488 bus, for asserting data received by said microprocessor port onto said IEEE 488 bus; said talker circuit means including a transparent latch for asserting and latching data received from said microprocessor port onto said IEEE 488 bus such that data received from said microprocessor port is asserted onto said IEEE 488 bus before the trailing edge of said write pulses; and source handshake means, coupled to said talker circuit means and said IEEE 488 bus, for asserting a data valid signal on said DAV line of said IEEE 488 bus after said talker circuit has asserted data on said IEEE 488 bus for a first predefined minimum settling period; said source handshake means including speedup means that, when enabled, asserts said signal on said DAV line of said IEEE 488 bus after said talker circuit has asserted data on said IEEE 488 bus for a second predefined settling period that is less than said first predefined minimum settling period; whereby speed of transmission of data by said microprocessor is improved by reducing said settling period.

Claim 10

The interface set forth in claim 6, said interface including an speedup enable switch for enabling said speedup means.

Claim 11

The interface set forth in claim 6, said microprocessor having an interrupt signal port; said microprocessor port including at least one line for transmitting interrupt signals to said interrupt signal port of said microprocessor; said acceptor handshake means including means for detecting when the last byte of a data transfer has been received from said IEEE 488 bus while said listener circuit means is transmitting data to said microprocessor via said microprocessor port and for then transmitting a first interrupt signal to said interrupt signal port of said microprocessor via said microprocessor port; and synchronization means, coupled to said IEEE 488 bus, for detecting when a data valid signal previously asserted on said DAV line is unasserted, including means for then transmitting a second interrupt signal to said interrupt signal port of said microprocessor via said microprocessor port; and a synchronization interrupt enable switch for enabling said synchronization means to send said second interrupt signal to said microprocessor; wherein said synchronization means does not send said second interrupt signal when a data valid signal previously asserted on said DAV line is unasserted unless said synchronization interrupt enable switch is enabled; whereby said microprocessor is automatically notified by said first interrupt signal that the last byte of a data transfer has been transmitted by said interface from said IEEE 488 bus to said microprocessor and said microprocessor is automatically notified by said second interrupt signal that all other devices on said IEEE 488 bus have accepted the last byte of a data transfer.

Claim 12

The interface set forth in claim 5, wherein said microprocessor includes an interrupt signal port; said microprocessor port including at least one line for transmitting interrupt signals to said interrupt signal port of said microprocessor; said IEEE 488 bus including a data valid (DAV) line; said acceptor handshake means including means for detecting when the last byte of a data transfer has been received from said IEEE 488 bus while said listener circuit means is transmitting data to said microprocessor via said microprocessor port and for then transmitting a first interrupt signal to said interrupt signal port of said microprocessor via said microprocessor port; said interface further including: synchronization means, coupled to said IEEE 488 bus, for detecting when a data valid signal previously asserted on said DAV line is unasserted, and for then transmitting a second interrupt signal to said interrupt signal port of said microprocessor via said microprocessor port; and a synchronization interrupt enable switch for enabling said synchronization means to send said second interrupt signal to said microprocessor; wherein said synchronization means does not send said second interrupt signal when a data valid signal previously asserted on said DAV line is unasserted unless said synchronization interrupt enable switch is enabled; said synchronization interrupt enable switch coupled to said microprocessor via said microprocessor port so that said microprocessor can enable and disable said synchronization interrupt enable switch; whereby said microprocessor is automatically notified by said first interrupt signal that the last byte of a data transfer has been transmitted by said interface from said IEEE 488 bus to said microprocessor and said microprocessor is automatically notified by said second interrupt signal that said IEEE 488 bus has completed the data transfer.

Claim 13

The interface set forth in claim 9, said interface including: talker circuit means, coupled to said microprocessor port and said IEEE 488 bus, for asserting data received by said microprocessor port onto said IEEE 488 bus; source handshake means, coupled to said talker circuit means and said IEEE 488 bus, for asserting a data valid signal on said DAV line of said IEEE 488 bus after said talker circuit has asserted data on said IEEE 488 bus and for reasserting said data valid signal in accordance with a predefined source handshake protocol; said synchronization means transmitting said second interrupt signal to said interrupt signal port of said microprocessor via said microprocessor port when said source handshaking means desserts said data valid signal on said DAV line and said synchronization interrupt enable switch is enabled.

Claim 14

The interface set forth in claim 10, wherein said microprocessor port includes a write line for receiving write pulses from said microprocessor; each said write pulses having a predefined duration and a tailing edge; said talker circuit means including a transparent latch for asserting and latching data received from said microprocessor port onto said IEEE 488 bus such that data received from said microprocessor port is asserted onto said IEEE 488 bus before the trailing edge of said write pulses; said talker circuit means including a transparent latch for asserting and latching data received from said microprocessor port onto said IEEE 488 bus such that data received from said microprocessor port is asserted onto said IEEE 488 bus before the trailing edge of said write pulses; source handshake means, coupled to said talker circuit means and said IEEE 488 bus, for asserting a signal on said DAV line of said IEEE 488 bus after said talker circuit has asserted data on said IEEE 488 bus for a first predefined minimum settling period; said source handshake means including speedup means that, when enabled, asserts said signal on said DAV line of said IEEE 488 bus after said talker circuit has asserted data on said IEEE 488 bus for a second predefined settling period that is less than said first predefined minimum settling period; and said interface including a speedup enable switch for enabling said speedup means; whereby speed of transmission of data by said microprocessor is improved by reducing said settling period.

Claim 15

The interface set forth in claim 5, wherein said microprocessor includes an interrupt signal port; said microprocessor port including at least one line for transmitting interrupt signals to said interrupt signal port of said microprocessor; said IEEE 488 bus including a data valid (DAV) line; said interface further including: talker circuit means, coupled to said microprocessor port and said IEEE 488 bus, for asserting data received by said microprocessor port onto said IEEE 488 bus; synchronization means, coupled to said IEEE 488 bus, for detecting when a data valid signal previously asserted on said DAV line is unasserted, and for then transmitting a synchronization interrupt signal to said interrupt signal port of said microprocessor via said microprocessor port; and a synchronization interrupt enable switch for enabling said source handshake means to send said synchronization interrupt signal to said microprocessor; wherein said synchronization means does not send said synchronization interrupt signal when a data valid signal previously asserted on said DAV line is unasserted unless said synchronization interrupt enable switch is enabled; whereby said microprocessor is automatically notified by said synchronization interrupt signal that said IEEE 488 bus has completed the data transfer.