Input/output cache

Claim 2

An input/output cache for use in a digital computer system having a plurality of input/output devices connected to an input/output bus, the cache comprising: a cache buffer connected to an input/output bus and to a main system memory, wherein the cache buffer is organized as a plurality of lines; a cache control register file having a plurality of registers, each cache control register corresponding to one of the cache buffer lines and containing a main memory address corresponding to the corresponding cache buffer line; a channel status register file having a plurality of channel status registers, each corresponding to a single input/output device attached to the input/output bus, and each channel status register containing a control field for selecting one of the cache control registers and its corresponding cache buffer line; means for selecting one of the channel status registers when the corresponding input/output bus; a comparator for comparing an address placed on the input/output bus, by an input/output device performing a data access, with the address contained in the cache control register selected by the selected channel status register control field, and for generating a cache hit signal if they match, else generating a cache hit signal; and means for, if a cache hit signal is generated, causing the input/output device to perform a data access of the corresponding cache buffer line.

Claim 3

The cache of claim 1, further comprising means for, if a cache miss is generated by the comparator, loading a new value into the channel status register control field for the channel status register corresponding to the input/output device performing a data access, wherein a different cache control register is selected by such channel status register, wherein one input/output device can select a second cache control register after a cache miss.

Claim 4

The cache of claim 1, further comprising a Translation Control Work (TCW) cache register file having a plurality of TCW cache registers, each corresponding to a cache control register, each TCW cache register containing a field which holds a main memory real page number corresponding to a virtual page number for the buffer line corresponding to that cache control register.

Claim 5

An input/output cache for use in a digital computer system, such system including a central processor, a main system memory, an input/output bus, and a plurality of input/output devices connected to the input/output bus, the cache comprising: a buffer memory containing data organized as a plurality of lines, wherein the buffer memory is connected to the main system memory for exchanging data therewith; a cache control memory for containing an identifying address indicating a location in main system memory corresponding to each of the buffer memory lines; means for assigning at least one of the buffer memory lines to a selected input/output device, wherein a line assigned to an input/output device is used for buffering data only for that input/output device, and wherein the selected input/output device accesses main system memory only through an assigned buffer memory line; means for assigning at least one of the buffer memory lines to the central processor, wherein the central processor accesses locations in the main system memory through an assigned buffer memory line; a comparator connected to the input/output bus and to the buffer memory, wherein the comparator compares identifying addresses from the cache control memory to addresses present on the input/output bus, and generates a cache hit signal if there is a match; control means for determining which input/output or central processor device has placed an address on the input/output bus, and for causing the comparator to compare an identifying address, corresponding to a buffer memory line assigned to the determined device, with an address on the input/output bus; and means for allowing an input/output device which has placed an address on the input/output bus to access a buffer line assigned to it when the comparator generates a cache hit signal.

Claim 6

An input/output cache for use in a digital computer system, such system including a central processor, a main system memory, an input/output bus, and a plurality of input/output devices connected to the input/output bus, the cache comprising: a buffer memory containing data organized as a plurality of lines, wherein the buffer memory is connected to the main system memory for exchanging data therewith; a cache control memory for containing an identifying address indicating a location in main system memory corresponding to each of the buffer memory lines; means for assigning at least one of the buffer memory lines to a selected input/output device, wherein a line assigned to an input/output device is used for buffering data only for that input/output device, and wherein the selected input/output device accesses main system memory only through an assigned buffer memory line; means for assigning at least one of the buffer memory lines to the central processor, wherein the central processor accesses locations in the main system memory through an assigned buffer memory line; a comparator connected to the input/output bus and to the buffer memory, wherein the comparator compares identifying addresses from the cache control memory to addresses present on the input/output bus, and generates a cache hit signal if there is a match; control means for determining which input/output or central processor device has placed an address on the input/output bus, and for causing the comparator to compare an identifying address, corresponding to a buffer memory line assigned to the determined device, with an address on the input/output bus; and means for allowing an input/output device which has placed an address on the input/output bus to access a buffer line assigned to it when the comparator generates a cache hit signal.

Claim 7

The cache of claim 4, wherein the control means further restricts the identifying addresses to a portion, less than all, of the addresses contained in the main system memory.

Claim 8

The cache of claim 4, wherein the main system memory corresponds to a first portion of a main memory address space, and wherein a bus memory is attached to and accessible over the input/output bus, and further wherein the bus memory corresponds to a second portion of the main memory address space.

Claim 9

The cache of claim 6, wherein addresses in the bus memory are accessed directly by the central processor and input/output devices, without transfer of data through the buffer memory.