Method and apparatus for transferring information over a common parallel bus using a fixed sequence of bus phase transitions

Claim 3

A method according to claim 1 wherein the placing of the first, second and third control signals on the bus is performed by the target.

Claim 4

A method according to claim 1 wherein when the bus is in the third information phase the status information comprises either: (a) an ACK signal, if data information is transferred during the second information phase and an error is not detected; or (b) a NAK signal, if data information is transferred during the second information phase and an error is detected.

Claim 5

A method according to claim 1, wherein the bus phases include a selection phase, the selection phase including a transfer of initiator ID and target ID information from the initiator to the target, and further comprising, when the bus is in the first information phase: (a) transferring a target ID and initiator ID to the target, the target having a target ID received during the selection phase and an initiator ID received during the selection phase; and (b) comparing the transferred target ID with the target ID received during the selection phase and comparing the transferred initiator ID with the initiator ID received during the selection phase.

Claim 6

A method according to claim 4 wherein the transferred destination ID and source ID are transferred as part of the header information.

Claim 7

A method according to claim 1 wherein the header information comprises a seven-byte format.

Claim 8

A method according to claim 1 wherein the header information comprises a number specifying the quantity of information bytes to be transferred in the second information phase, the information bytes forming a portion of the data information.

Claim 9

A method according to claim 7 wherein the number specifying the quantity of information bytes to be transferred in the second information phase is arranged in a two-byte format.

Claim 10

A method according to claim 1 wherein the header information comprises a data link operation code.

Claim 11

A method according to claim 1 wherein the header information comprises a REQ/ACK offset.

Claim 12

A method according to claim 1 wherein the header information comprises destination ID information.

Claim 13

A method according to claim 1 wherein the header information comprises source ID information.

Claim 14

A method according to claim 1 wherein the header information comprises a checksum.

Claim 15

A method according to claim 1 wherein the header information comprises: (a) a data link operation code; (b) a REQ/ACK offset; (c) destination ID information; (d) source ID information; (e) a number specifying the quantity of information bytes to be transferred in the second information phase, the information bytes forming a portion of the data information; and (f) a checksum.

Claim 16

A method according to claim 1 wherein the status information comprises a one-byte format.

Claim 17

A method according to claim 1 wherein the data information comprises an operation mode.

Claim 18

A method according to claim 1 wherein the data information comprises a flags byte.

Claim 19

A method according to claim 1 wherein the data information comprises one or more information bytes.

Claim 20

A method according to claim 1 wherein the data information comprises a checksum.

Claim 21

A method according to claim 1 wherein the data information comprises: (a) an operation code; (b) a flags byte; (c) one or more information bytes; and (d) a checksum.

Claim 22

A method according to claim 1 wherein the target comprises a first state machine, the state machine including states which correspond to the first, second and third information phases of the bus.

Claim 23

A method according to claim 21 wherein the first state machine enables a second state machine, the second state machine controlling the target's preparation for transferring information over the bus.

Claim 24

A method according to claim 22 wherein the first state machine further enables a third state machine, the third state machine controlling the operation of the target in receiving information in the first and second information phases and in sending information in the third information phase.

Claim 25

A method according to claim 21 wherein the first state machine enables a third state machine, the third state machine controlling the operation of the target in receiving information in the first and second information phases and in sending information in the third information phase.

Claim 26

A method according to claim 1 wherein the initiator comprises a first state machine, the state machine including states which correspond to the first, second and third information phases of the bus.

Claim 27

A method according to claim 25 wherein the first state machine enables a second state machine, the second state machine controlling the initiator's preparation for transferring information over the bus.

Claim 28

A method according to claim 26 wherein the first state machine further enables a third state machine, the third state machine controlling the operation of the initiator in sending information in the first and second information phases and in receiving information in the third information phase.

Claim 29

A method according to claim 25 wherein the first state machine enables a third state machine, the third state machine controlling the operation of the initiator in sending information in the first and second information phases and in receiving information in the third information phase.

Claim 30

A method according to claim 1 further comprising when the bus is in the first information phase: (a) transferring a first value from the initiator to the target, the target having associated with it a second value; (b) comparing the first value with the second value; and (c) selecting the smaller of the first and second values as a REQ/ACK offset value for an information transfer.

Claim 31

A method according to claim 29 wherein the first value is a maximum REQ/ACK offset value of the initiator.

Claim 32

A method according to claim 29 wherein the second value corresponds to the size of a buffer in the target.

Claim 33

A method according to claim 29 wherein the first value forms a portion of the header information.

Claim 34

A method according to claim 1 wherein the data information comprises command information.

Claim 37

A method according to claim 34 wherein the placing of the first, second and third control signals on the bus is performed by the target.

Claim 38

A method according to claim 34 wherein when the bus is in the third information phase the status information comprises either: (a) an ACK signal, if data information is transferred during the second information phase and an error is not detected; or (b) a NAK signal, if data information is transferred during the second information phase and an error is detected.

Claim 39

A method according to claim 34, wherein the bus phases include a selection phase, the selection phase including a transfer of initiator ID and target ID information from the initiator to the target, and further comprising when the bus is in the first information phase, transferring an initiator ID and target ID to the target, the target having an initiator ID received during the selection phase and a target ID received during the selection phase; wherein the step of monitoring the transfer of header information comprises comparing the transferred target ID with the target ID received during the selection phase and comparing the transferred initiator ID with the initiator ID received during the selection phase.

Claim 40

A method according to claim 34 wherein the header information comprises a seven-byte format.

Claim 41

A method according to claim 34 wherein the header information comprises a number specifying the quantity of information bytes to be transferred in the second information phase, the information bytes forming a portion of the data information.

Claim 42

A method according to claim 39 wherein the number specifying the quantity of information bytes to be transferred in the second information phase is arranged in a two-byte format.

Claim 43

A method according to claim 34 wherein the header information comprises a data link operation code.

Claim 44

A method according to claim 34 wherein the header information comprises a REQ/ACK offset.

Claim 45

A method according to claim 34 wherein the header information comprises destination ID information.

Claim 46

A method according to claim 34 wherein the header information comprises source ID information.

Claim 47

A method according to claim 34 wherein the header information comprises a checksum.

Claim 48

A method according to claim 34 wherein the header information comprises: (a) a data link operation code; (b) a REQ/ACK offset; (c) destination ID information; (d) source ID information; (e) a number specifying the quantity of information bytes to be transferred in the second information phase, the information bytes forming a portion of the data information; and (f) a checksum.

Claim 49

A method according to claim 34 wherein the status information comprises a one-byte format.

Claim 50

A method according to claim 34 wherein the data information comprises an operation mode.

Claim 51

A method according to claim 34 wherein the data information comprises a flags byte.

Claim 52

A method according to claim 34 wherein the data information comprises one or more information bytes.

Claim 53

A method according to claim 34 wherein the data information comprises a checksum.

Claim 54

A method according to claim 34 wherein the data information comprises: (a) an operation code; (b) a flags byte; (c) one or more information bytes; and (d) a checksum.

Claim 55

A method according to claim 34 wherein the target comprises a first state machine, the state machine including states which correspond to the first, second and third information phases of the bus.

Claim 56

A method according to claim 53 wherein the first state machine enables a third state machine, the third state machine controlling the operation of the target in receiving information in the first and second information phases and in sending information in the third information phase.

Claim 57

A method according to claim 53 wherein the first state machine enables a second state machine, the second state machine controlling the target's preparation for transferring information over the bus.

Claim 58

A method according to claim 55 wherein the first state machine further enables a third state machine, the third state machine controlling the operation of the target in receiving information in the first and second information phases and in sending information in the third information phase.

Claim 59

A method according to claim 34 wherein the initiator comprises a first state machine, the state machine including states which correspond to the first, second and third information phases of the bus.

Claim 60

A method according to claim 57 wherein the first state machine enables a second state machine, the second state machine controlling the initiator's preparation for transferring information over the bus.

Claim 61

A method according to claim 58 wherein the first state machine further enables a third state machine, the third state machine controlling the operation of the initiator in sending information in the first and second information phases and in receiving information in the third information phase.

Claim 62

A method according to claim 57 wherein the first state machine enables a third state machine, the third state machine controlling the operation of the initiator in sending information in the first and second information phases and in receiving information in the third information phase.

Claim 63

A method according to claim 34 further comprising when the bus is in the first information phase: (a) transferring a first value from the initiator to the target, the target having associated with it a second value; (b) comparing the first value with the second value; and (c) selecting the smaller of the first and second values as a REQ/ACK offset value for an information transfer.

Claim 64

A method according to claim 61 wherein the first value is a maximum REQ/ACK offset value of the initiator.

Claim 65

A method according to claim 61 wherein the second value corresponds to the size of a buffer in the target.

Claim 66

A method according to claim 61 wherein the first value forms a portion of the header information.

Claim 67

A method according to claim 34 wherein the data information comprises command information.

Claim 68

A computer system comprising a system bus and two or more devices coupled to said bus, one of the devices being an initiator and another being a target, said bus comprising separate data and control lines, and operating according to a sequence of bus phases including information phases to allow for a transfer of information between the initiator and the target, the information phases comprising a first information phase allowing the transfer of header information from the initiator to the target over said bus, a second information phase allowing the transfer of data information from the initiator to the target over said bus, and a third information phase allowing the transfer of status information from the target to the initiator over said bus, the initiator comprising: (a) an information phase control signal receiver coupled to one or more of the control lines of said bus to receive information phase control signals transmitted from the target over the one or more control lines, the information phase control signals consisting of a first control signal to indicate said bus is in the first information phase, a second control signal to indicate said bus has transitioned from the first information phase to the second information phase, and a third control signal to indicate said bus has transitioned from the second information phase to the third information phase: (b) an information transmitter coupled to the data lines of said bus to transmit to the target header information during the first information phase and data information during the second information phase; (c) a status receiver coupled to the data lines of said bus to receive from the target status information during the third information phase; and the target comprising: (a) an information phase control signal generator coupled to one or more of the control lines of said bus to generate information phase control signals for transmission to the initiator over the one or more control lines, the information phase control signals consisting of a first control signal to indicate said bus is in the first information phase, a second control signal to indicate said bus has transitioned from the first information phase to the second information phase, and a third control signal to indicate said bus has transitioned from the second information phase to the third information phase; (b) an information receiver coupled to the data lines of said bus to receive from the initiator header information during the first information phase and data information during the second information phase; and (c) a status transmitter coupled to the data lines of said bus to transmit from the target to the initiator status information during the third information phase; (d) the information phase control signal generator consisting of an information phase transition signal generator controlling generation of the information phase control signals according to a fixed preselected order of information phase transitions to cause all transfers of information between the initiator and the target during the information transfer phases always to occur only in the order of header information from the initiator to the target, data information from the initiator to the target and status information from the target to the initiator, the order being independent of the configuration of the initiator and the target and independent of the type of information transfer.

Claim 69

A computer system comprising a system bus and two or more devices coupled to said bus, one of the devices being an initiator and another being a target, said bus comprising separate data and control lines, and operating according to a sequence of bus phases including information phases to allow for a transfer of information between the initiator and the target, the information phases comprising a first information phase allowing the transfer of header information from the initiator to the target over said bus, a second information phase allowing the transfer of data information from the initiator to the target over said bus, and a third information phase allowing the transfer of status information from the target to the initiator over said bus, the initiator comprising: (a) an information phase control signal receiver coupled to one or more of the control lines of said bus to receive information phase control signals transmitted from the target over the one or more control lines, the information phase control signals consisting of a first control signal to indicate said bus is in the first information phase, a second control signal to indicate said bus has transitioned from the first information phase to the second information phase, and a third control signal to indicate said bus has transitioned from the second information phase to the third information phase: (b) an information transmitter coupled to the data lines of said bus to transmit to the target header information during the first information phase and data information during the second information phase; (c) a status receiver coupled to the data lines of said bus to receive from the target status information during the third information phase; and the target comprising: (a) an information phase control signal generator coupled to one or more of the control lines of said bus to generate information phase control signals for transmission to the initiator over the one or more control lines, the information phase control signals consisting of a first control signal to indicate said bus is in the first information phase, a second control signal to indicate said bus has transitioned from the first information phase to the second information phase, and a third control signal to indicate said bus has transitioned from the second information phase to the third information phase; (b) an information receiver coupled to the data lines of said bus to receive from the initiator header information during the first information phase and data information during the second information phase; and (c) a status transmitter coupled to the data lines of said bus to transmit from the target to the initiator status information during the third information phase; (d) the information phase control signal generator consisting of an information phase transition signal generator controlling generation of the information phase control signals according to a fixed preselected order of information phase transitions to cause all transfers of information between the initiator and the target during the information transfer phases always to occur only in the order of header information from the initiator to the target, data information from the initiator to the target and status information from the target to the initiator, the order being independent of the configuration of the initiator and the target and independent of the type of information transfer.

Claim 70

A computer system comprising a system bus and two or more devices coupled to said bus, one of the devices being an initiator and another being a target, said bus comprising separate data and control lines, and operating according to a sequence of bus phases including a selection phase and information phases to allow for a transfer of information between the initiator and the target, the selection phase including a transfer of initiator ID and target ID information from the initiator to the target and the information phases comprising a first information phase allowing the transfer of header information from the initiator to the target over said bus, a second information phase allowing the transfer of data information from the initiator to the target over said bus, and a third information phase allowing the transfer of status information from the target to the initiator over said bus, the initiator comprising: (a) an information phase control signal receiver coupled to one or more of the control lines of said bus to receive information phase control signals transmitted from the target over the one or more control lines, the information phase control signals consisting of a first control signal to indicate said bus is in the first information phase, a second control signal to indicate said bus has transitioned to the second information phase, and a third control signal to indicate said bus has transitioned to the third information phase; (b) an information transmitter coupled to the data lines of said bus to transmit from the target header information during the first information phase and data information during the second information phase; (c) a status receiver coupled to the data lines of said bus to receive from the target status information during the third information phase; and the target comprising: (d) an information phase control signal generator coupled to one or more of the control lines of said bus to generate information phase control signals for transmission to the initiator over the one or more control lines, the information phase control signals consisting of a first control signal to indicate said bus is in the first information phase, a second control signal to indicate said bus has transitioned to the second information phase, and a third control signal to indicate said bus has transitioned to the third information phase; (b) an information receiver coupled to the data lines of said bus to receive from the initiator header information during the first information phase and data information during the second information phase; and (c) a status transmitter coupled to the data lines of said bus to transmit from the target to the initiator status information during the third information phases; (d) a comparator, coupled to said information receiver, to compare an initiator ID received as a part of header information during the first information phase with the initiator ID received during the selection phase and to compare a target ID received as part of header information during the first information phase with the target ID received during the selection phase to determine if one or more error conditions have occurred; (e) the information phase control signal generator generating the information phase control signals in response to the determination of the comparator to cause, (i) if the one or more error conditions have not occurred, the information transferred between the initiator and the target during the information transfer phases always to occur only in the order of header information from the initiator to the target, data information from the initiator to the target and status information from the target to the initiator; and (ii) if the one or more error conditions have occurred, the information transferred between the initiator and the target during the information transfer phases always to occur only in the order of header information from the initiator to the target and status information from the target to the initiator; the order of phase transitions of (i) and (ii) being independent of the configuration of the initiator and the target and independent of the type of information transfer.

Claim 71

A computer system comprising a system bus and two or more devices coupled to said bus, one of the devices being an initiator and another being a target, said bus comprising separate data and control lines, and operating according to a sequence of bus phases including a selection phase and information phases to allow for a transfer of information between the initiator and the target, the selection phase including a transfer of initiator ID and target ID information from the initiator to the target and the information phases comprising a first information phase allowing the transfer of header information from the initiator to the target over said bus, a second information phase allowing the transfer of data information from the initiator to the target over said bus, and a third information phase allowing the transfer of status information from the target to the initiator over said bus, the initiator comprising: (a) an information phase control signal receiver coupled to one or more of the control lines of said bus to receive information phase control signals transmitted from the target over the one or more control lines, the information phase control signals consisting of a first control signal to indicate said bus is in the first information phase, a second control signal to indicate said bus has transitioned to the second information phase, and a third control signal to indicate said bus has transitioned to the third information phase; (b) an information transmitter coupled to the data lines of said bus to transmit from the target header information during the first information phase and data information during the second information phase; (c) a status receiver coupled to the data lines of said bus to receive from the target status information during the third information phase; and the target comprising: (d) an information phase control signal generator coupled to one or more of the control lines of said bus to generate information phase control signals for transmission to the initiator over the one or more control lines, the information phase control signals consisting of a first control signal to indicate said bus is in the first information phase, a second control signal to indicate said bus has transitioned to the second information phase, and a third control signal to indicate said bus has transitioned to the third information phase; (b) an information receiver coupled to the data lines of said bus to receive from the initiator header information during the first information phase and data information during the second information phase; and (c) a status transmitter coupled to the data lines of said bus to transmit from the target to the initiator status information during the third information phases; (d) a comparator, coupled to said information receiver, to compare an initiator ID received as a part of header information during the first information phase with the initiator ID received during the selection phase and to compare a target ID received as part of header information during the first information phase with the target ID received during the selection phase to determine if one or more error conditions have occurred; (e) the information phase control signal generator generating the information phase control signals in response to the determination of the comparator to cause, (i) if the one or more error conditions have not occurred, the information transferred between the initiator and the target during the information transfer phases always to occur only in the order of header information from the initiator to the target, data information from the initiator to the target and status information from the target to the initiator; and (ii) if the one or more error conditions have occurred, the information transferred between the initiator and the target during the information transfer phases always to occur only in the order of header information from the initiator to the target and status information from the target to the initiator; the order of phase transitions of (i) and (ii) being independent of the configuration of the initiator and the target and independent of the type of information transfer.

Claim 72

A target device for coupling to a common parallel bus, the bus having coupled thereto an initiator device, the bus having separate data and control lines, and the bus operating according to a sequence of bus phases including information phases to allow for a transfer of information between the initiator device and the target device, the information phases comprising a first information phase allowing the transfer of header information over the bus, a second information phase allowing the transfer of data information over the bus, and a third information phase allowing the transfer of status information over the bus, said target device comprising: (a) an information phase control signal generator, for coupling to one or more of the control lines of the bus to generate information phase control signals for transmission from the target device to the initiator device over the one or more control lines, the information phase control signals consisting of a first control signal to indicate the bus is in the first information phase, a second control signal to indicate the bus has transitioned from the first information phase to the second information phase, and a third control signal to indicate the bus has transitioned from the second information phase to the third information phase; (b) an information receiver, for coupling to the data lines of the bus to receive header information at the target device from the initiator device during the first information phase and data information during the second information phase; and (c) a status transmitter, for coupling to the data lines of the bus to transmit status information from the target device to the initiator device during the third information phase; (d) the information phase control signal generator consisting of an information phase transition signal generator controlling generation of the information phase control signals to cause all transfers of information between the initiator device and the target device during the information transfer phases always to occur only in the order to header information from the initiator device to the target device, data information from the initiator device to the target device and status information from the target device to the initiator device, the order being independent of the configuration of the initiator and the target and independent of the type of information transfer.

Claim 73

A target device for coupling to a common parallel bus, the bus having coupled thereto an initiator device, the bus having separate data and control lines, and the bus operating according to a sequence of bus phases including information phases to allow for a transfer of information between the initiator device and the target device, the information phases comprising a first information phase allowing the transfer of header information over the bus, a second information phase allowing the transfer of data information over the bus, and a third information phase allowing the transfer of status information over the bus, said target device comprising: (a) an information phase control signal generator, for coupling to one or more of the control lines of the bus to generate information phase control signals for transmission from the target device to the initiator device over the one or more control lines, the information phase control signals consisting of a first control signal to indicate the bus is in the first information phase, a second control signal to indicate the bus has transitioned from the first information phase to the second information phase, and a third control signal to indicate the bus has transitioned from the second information phase to the third information phase; (b) an information receiver, for coupling to the data lines of the bus to receive header information at the target device from the initiator device during the first information phase and data information during the second information phase; and (c) a status transmitter, for coupling to the data lines of the bus to transmit status information from the target device to the initiator device during the third information phase; (d) the information phase control signal generator consisting of an information phase transition signal generator controlling generation of the information phase control signals to cause all transfers of information between the initiator device and the target device during the information transfer phases always to occur only in the order to header information from the initiator device to the target device, data information from the initiator device to the target device and status information from the target device to the initiator device, the order being independent of the configuration of the initiator and the target and independent of the type of information transfer.

Claim 74

A target device according to claim 68, wherein the bus phases include a selection phase and further comprising a comparator, coupled to said information receiver, to compare an initiator ID received as part of header information during the first information phase with an initiator ID received during the selection phase and to compare a target ID received as part of header information during the first information phase with a target ID received during the selection phase.

Claim 75

A target device according to claim 68, wherein said control signal generator comprises a first state machine having at least first, second and third states, and wherein the generation of the first control signal is responsive to said first state machine being in the first state, the generation of the second control signal is responsive to said first state machine being in the second state, and the generation of the third control signal is responsive to said first state machine being in the third state.

Claim 76

A target device according to claim 70 wherein said status transmitter is responsive to said first state machine such that status transmitter is adapted to transmitted status information when said first state machine is in the third state.

Claim 77

A target device according to claim 70 wherein said information receiver is responsive to said state machine such that said information receiver is adapted to receive the header information and the data information when said state machine is in the first and second states, respectively.

Claim 78

A target device according to claim 68 wherein the header information comprises a data link operation code.

Claim 79

A target device according to claim 68 wherein the header information comprises a REQ/ACK offset.

Claim 80

A target device according to claim 68 wherein the header information comprises destination ID information.

Claim 81

A target device according to claim 68 wherein the header information comprises source ID information.

Claim 82

A target device according to claim 68 wherein the header information comprises a number specifying the quantity of information bytes to be transferred in the second information phase, said information bytes forming a portion of the data information.

Claim 83

A target device according to claim 68 wherein the header information comprises a checksum.

Claim 84

A target device according to claim 68 wherein the header information comprises: (a) a data link operation code; (b) a REQ/ACK offset; (c) destination ID information; (d) source ID information; (e) a number specifying the quantity of information bytes to be transferred during the second information phase, said information bytes forming a portion of the data information; and (f) a checksum.

Claim 85

A target device according to claim 68 wherein the data information comprises an operation code.

Claim 86

A method according to claim 68 wherein the data information comprises a flags byte.

Claim 87

A method according to claim 68 wherein the data information comprises one or more information bytes.

Claim 88

A method according to claim 68 wherein the data information comprises a checksum.

Claim 89

A method according to claim 68 wherein the data information comprises: (a) an operation code; (b) a flags byte; (c) one or more information bytes; and (d) a checksum.

Claim 90

A target device according to claim 68 wherein the target device comprises a mass storage device.

Claim 91

A target device according to claim 68 wherein the target device comprises an interface.

Claim 92

A target device according to claim 68 further comprising a REQ/ACK offset selector, coupled to said information receiver, for selecting the smaller of: (i) a first value received from the initiator device, and (ii) a second value associated with said target device as a REQ/ACK offset for said target device.

Claim 93

A target device according to claim 87 wherein the first value is a maximum REQ/ACK offset value of the initiator device.

Claim 94

A target device according to claim 88 wherein the second value corresponds to the size of a buffer in said target device.

Claim 95

A target device according to claim 87 wherein the first value forms a portion of the header information.

Claim 96

A target device according to claim 68 wherein the data information comprises command information.

Claim 97

An initiator device for coupling to a common parallel bus, the bus having coupled thereto a target device, the bus having separate data and control lines, and the bus operating according to a sequence of bus phases including information phases to allow for a transfer of information between the initiator device and the target device, the information phases comprising a first information phase allowing the transfer of header information over the bus, a second information phase allowing the transfer of data information over the bus, and a third information phase allowing the transfer of status information over the bus, said initiator device comprising: (a) an information phase control signal receiver, for coupling to one or more of the control lines of the bus to receive information phase control signals transmitted from the target device to the initiator device over the one or more control lines, the information phase control signals consisting of a first control signal to indicate the bus is in the first information phase, a second control signal to indicate the bus has transitioned from the first information phase to the second information phase, and a third control signal to indicate the bus has transitioned from the second information phase to the third information phase; (b) an information transmitter, coupled to the data lines of the bus to transmit header information to the target device during the first information phase and data information during the second information phase; and (c) a status receiver, coupled to the data lines of the bus to receive status information from the target device during the third information phase; (d) the information phase control signal receiver consisting of a signal receiver arranged to receive information phase control signals in a fixed preselected order such that all transfers of information between the initiator device and the target device during the information transfer phases always to occur only in the order of header information from the initiator device to the target device, data information from the initiator device to the target device and status information from the target device to the initiator device, the order being independent of the configuration of the initiator and the target and independent of the type of information transfer.

Claim 98

An initiator device for coupling to a common parallel bus, the bus having coupled thereto a target device, the bus having separate data and control lines, and the bus operating according to a sequence of bus phases including information phases to allow for a transfer of information between the initiator device and the target device, the information phases comprising a first information phase allowing the transfer of header information over the bus, a second information phase allowing the transfer of data information over the bus, and a third information phase allowing the transfer of status information over the bus, said initiator device comprising: (a) an information phase control signal receiver, for coupling to one or more of the control lines of the bus to receive information phase control signals transmitted from the target device to the initiator device over the one or more control lines, the information phase control signals consisting of a first control signal to indicate the bus is in the first information phase, a second control signal to indicate the bus has transitioned from the first information phase to the second information phase, and a third control signal to indicate the bus has transitioned from the second information phase to the third information phase; (b) an information transmitter, coupled to the data lines of the bus to transmit header information to the target device during the first information phase and data information during the second information phase; and (c) a status receiver, coupled to the data lines of the bus to receive status information from the target device during the third information phase; (d) the information phase control signal receiver consisting of a signal receiver arranged to receive information phase control signals in a fixed preselected order such that all transfers of information between the initiator device and the target device during the information transfer phases always to occur only in the order of header information from the initiator device to the target device, data information from the initiator device to the target device and status information from the target device to the initiator device, the order being independent of the configuration of the initiator and the target and independent of the type of information transfer.

Claim 99

An initiator device according to claim 92 wherein said control signal receiver comprises a first state machine having at least first, second and third states, and wherein said first state machine is in the first state in response to the first control signal received from the target device, in the second state in response to the second control signal received from the target device and in the third state in response to the third control signal received from the target device.

Claim 100

An initiator device according to claim 93 wherein said information transmitter is responsive to said first state machine such that said information transmitter is adapted to transmit header information when said first state machine is in the first state and data information when said first state machine is in the second state.

Claim 101

An initiator device according to claim 93 wherein said status receiver is responsive to said state machine such that the status receiver is adapted to receive said status information when said state machine is in the third state.

Claim 102

A target device according to claim 92 wherein the header information comprises a data link operation code.

Claim 103

A target device according to claim 92 wherein the header information comprises a REQ/ACK offset.

Claim 104

A target device according to claim 92 wherein the header information comprises destination ID information.

Claim 105

A target device according to claim 92 wherein the header information comprises source ID information.

Claim 106

A initiator device according to claim 92 wherein the header information comprises a number specifying the quantity of information bytes to be transferred in the second information phase, said information bytes forming a portion of the data information.

Claim 107

A target device according to claim 92 wherein the header information comprises a checksum.

Claim 108

A target device according to claim 92 wherein the header information comprises: (a) a data link operation code; (b) a REQ/ACK offset; (c) destination ID information; (d) source ID information; (e) a number specifying the quantity of information bytes to be transferred during the second information phase, said information bytes forming a portion of the data information; and (f) a checksum.

Claim 109

An initiator device according to claim 92 wherein the data information comprises an operation code.

Claim 110

An initiator according to claim 92 wherein the data information comprises a flags byte.

Claim 111

An initiator according to claim 92 wherein the data information comprises one or more information bytes.

Claim 112

An initiator according to claim 92 wherein the data information comprises a checksum.

Claim 113

An initiator according to claim 92 wherein the data information comprises: (a) an operation code; (b) a flags byte; (c) one or more information bytes; and (d) a checksum.

Claim 114

An initiator device according to claim 92 wherein the initiator device comprises a mass storage device.

Claim 115

An initiator device according to claim 92 wherein the initiator device comprises an interface.

Claim 116

An initiator device according to claim 92 wherein the data information comprises command information.

Claim 117

A target device for coupling to a common parallel bus, the bus having coupled thereto an initiator device, the bus having separate data and control lines, and the bus operating according to a sequence of bus phases including a selection phase and information phases to allow for a transfer of information between the initiator device and the target device, the selection phase including a transfer of initiator ID and target ID information from the initiator to the target and the information phases comprising a first information phase allowing the transfer of header information over the bus, a second information phase allowing the transfer of data information over the bus, and a third information phase allowing the transfer of status information over the bus, the target device comprising: (a) an information phase control signal generator, for coupling to one or more of the control lines of the bus to generate information phase control signals for transmission to the initiator device over the one or more control lines, the information phase control signals consisting of a first control signal to indicate the bus is in the first information phase, a second control signal to indicate the bus has transitioned to the second information phase, and a third control signal to indicate the bus has transitioned to the third information phase; (b) an information receiver, for coupling to the data lines of the bus to receive from the initiator device header information during the first information phase and data information during the second information phase; (c) a status transmitter, for coupling to the data lines of the bus to transmit to the initiator device status information during the third information phase; (d) a comparator, coupled to said information receiver, to compare an initiator ID received as a part of header information during the first information phase with the initiator ID received during the selection phase and to compare a target ID received as part of header information during the first information phase with the target ID received during the selection phase to determine if one or more error conditions have occurred; (e) the information phase control signal generator generating the information phase control signals in response to the determination of the comparator to cause, (i) if the one or more error conditions have not occurred, the information transferred between the initiator and the target devices during the information transfer phases always to occur only in the order of header information from the initiator device to the target device, data information from the initiator device to the target device and status information from the target device to the initiator device; and (ii) if the one or more error conditions have occurred, the information transferred between the initiator and the target devices during the information transfer phases away to occur only in the order of header information from the initiator device to the target device and status information from the target device to the initiator device; the order of phase transitions of (i) and (ii) being independent of the configuration of the initiator and the target and independent of the type of information transfer.

Claim 118

A target device for coupling to a common parallel bus, the bus having coupled thereto an initiator device, the bus having separate data and control lines, and the bus operating according to a sequence of bus phases including a selection phase and information phases to allow for a transfer of information between the initiator device and the target device, the selection phase including a transfer of initiator ID and target ID information from the initiator to the target and the information phases comprising a first information phase allowing the transfer of header information over the bus, a second information phase allowing the transfer of data information over the bus, and a third information phase allowing the transfer of status information over the bus, the target device comprising: (a) an information phase control signal generator, for coupling to one or more of the control lines of the bus to generate information phase control signals for transmission to the initiator device over the one or more control lines, the information phase control signals consisting of a first control signal to indicate the bus is in the first information phase, a second control signal to indicate the bus has transitioned to the second information phase, and a third control signal to indicate the bus has transitioned to the third information phase; (b) an information receiver, for coupling to the data lines of the bus to receive from the initiator device header information during the first information phase and data information during the second information phase; (c) a status transmitter, for coupling to the data lines of the bus to transmit to the initiator device status information during the third information phase; (d) a comparator, coupled to said information receiver, to compare an initiator ID received as a part of header information during the first information phase with the initiator ID received during the selection phase and to compare a target ID received as part of header information during the first information phase with the target ID received during the selection phase to determine if one or more error conditions have occurred; (e) the information phase control signal generator generating the information phase control signals in response to the determination of the comparator to cause, (i) if the one or more error conditions have not occurred, the information transferred between the initiator and the target devices during the information transfer phases always to occur only in the order of header information from the initiator device to the target device, data information from the initiator device to the target device and status information from the target device to the initiator device; and (ii) if the one or more error conditions have occurred, the information transferred between the initiator and the target devices during the information transfer phases away to occur only in the order of header information from the initiator device to the target device and status information from the target device to the initiator device; the order of phase transitions of (i) and (ii) being independent of the configuration of the initiator and the target and independent of the type of information transfer.

Claim 119

A target device according to claim 111 wherein the header information comprises: (a) a data link operation code; (b) a REQ/ACK offset; (c) destination ID information; (d) source ID information; (e) a number specifying the quantity of information bytes to be transferred during the second information phase, said information bytes forming a portion of the data information; and (f) a checksum.

Claim 120

A target device according to claim 111 wherein the data information comprises: (a) an operation code; (b) a flags byte; (c) one or more information bytes; and (d) a checksum.

Claim 121

A target device according to claim 111 wherein the data information comprises command information.

Claim 122

A target device for coupling to a common parallel bus, the bus having coupled thereto an initiator device, the bus having separate data and control lines, and the bus operating according to a sequence of bus phases including information phases to allow for a transfer of information between the initiator device and the target device, the information phases comprising a first information phase allowing the transfer of header information over the bus, a second information phase allowing the transfer of data information over the bus, and a third information phase allowing the transfer of status information over the bus, said target device comprising: (a) means for placing a first control signal on one or more control lines indicating the bus is in the first information phase; (b) means responsive to the bus being in the first information phase to receive header information over said bus from the initiator device; (c) means for placing a second control signal on one or more control lines indicating the bus is in the second information phase, the bus having transitioned from the first information phase; (d) means responsive to the bus being in the second information phase to receive data information over the bus from the initiator device; (e) means for placing a third control signal on one or more control lines indicating the bus is in the third information phase, the bus having transitioned from the second information phase to the third information phase; (f) means responsive to the bus being in the third information phase to transfer status information over the bus from the target device to the initiator device; and (g) means for controlling the means for placing a first control signal, the means for placing a second control signal and the means for placing a third control signal according to a fixed preselected order of information phase transitions to cause all transfers of information between the target device and the initiator device during the information transfer phases always to occur only in the order of header information from the initiator device to the target device, data information from the initiator device to the target device and status information from the target device to the initiator device, the order being independent of the configuration of the initiator and the target and independent of the type of information transfer.

Claim 123

A target device for coupling to a common parallel bus, the bus having coupled thereto an initiator device, the bus having separate data and control lines, and the bus operating according to a sequence of bus phases including information phases to allow for a transfer of information between the initiator device and the target device, the information phases comprising a first information phase allowing the transfer of header information over the bus, a second information phase allowing the transfer of data information over the bus, and a third information phase allowing the transfer of status information over the bus, said target device comprising: (a) means for placing a first control signal on one or more control lines indicating the bus is in the first information phase; (b) means responsive to the bus being in the first information phase to receive header information over said bus from the initiator device; (c) means for placing a second control signal on one or more control lines indicating the bus is in the second information phase, the bus having transitioned from the first information phase; (d) means responsive to the bus being in the second information phase to receive data information over the bus from the initiator device; (e) means for placing a third control signal on one or more control lines indicating the bus is in the third information phase, the bus having transitioned from the second information phase to the third information phase; (f) means responsive to the bus being in the third information phase to transfer status information over the bus from the target device to the initiator device; and (g) means for controlling the means for placing a first control signal, the means for placing a second control signal and the means for placing a third control signal according to a fixed preselected order of information phase transitions to cause all transfers of information between the target device and the initiator device during the information transfer phases always to occur only in the order of header information from the initiator device to the target device, data information from the initiator device to the target device and status information from the target device to the initiator device, the order being independent of the configuration of the initiator and the target and independent of the type of information transfer.

Claim 124

A target device according to claim 115 wherein the data information comprises command information.

Claim 125

An initiator device adapted to be coupled to a common parallel bus, the bus having coupled thereto a target device, the bus having separate data and control lines, and the bus operating according to a sequence of bus phases including information phases to allow for a transfer of information between the initiator device and the target device, the information phases comprising a first information phase allowing the transfer of header information over the bus, a second information phase allowing the transfer of data information over the bus, and a third information phase allowing the transfer of status information over the bus, said initiator device comprising: (a) means for transferring header information over the bus to the target device in response to a first control signal placed on one or more control lines by the target device indicating the bus is in the first information phase; (b) means for transferring data information over the bus to the target device in response to a second control signal on one or more control lines indicating the bus is in the second information phase, the bus having transitioned from the first information phase; (c) means for receiving status information over the bus from the target device in response to a third control signal on one or more control lines indicating the bus is in the third information phase, the bus having transitioned from the second information phase to the third information phase; and (d) means for controlling the means for transferring header information, the means for transferring data information and the means for receiving status information to cause all transfers of information between the initiator device and the target device during the information transfer phases always to occur only in a preselected order of header information from the initiator device to the target device, data information from the initiator device to the target device and status information from the target device to the initiator device, the order being independent of the configuration of the initiator and the target and independent of the type of information transfer.

Claim 126

An initiator device adapted to be coupled to a common parallel bus, the bus having coupled thereto a target device, the bus having separate data and control lines, and the bus operating according to a sequence of bus phases including information phases to allow for a transfer of information between the initiator device and the target device, the information phases comprising a first information phase allowing the transfer of header information over the bus, a second information phase allowing the transfer of data information over the bus, and a third information phase allowing the transfer of status information over the bus, said initiator device comprising: (a) means for transferring header information over the bus to the target device in response to a first control signal placed on one or more control lines by the target device indicating the bus is in the first information phase; (b) means for transferring data information over the bus to the target device in response to a second control signal on one or more control lines indicating the bus is in the second information phase, the bus having transitioned from the first information phase; (c) means for receiving status information over the bus from the target device in response to a third control signal on one or more control lines indicating the bus is in the third information phase, the bus having transitioned from the second information phase to the third information phase; and (d) means for controlling the means for transferring header information, the means for transferring data information and the means for receiving status information to cause all transfers of information between the initiator device and the target device during the information transfer phases always to occur only in a preselected order of header information from the initiator device to the target device, data information from the initiator device to the target device and status information from the target device to the initiator device, the order being independent of the configuration of the initiator and the target and independent of the type of information transfer.

Claim 127

An initiator device according to claim 117 wherein the data information comprises command information.

Claim 128

A target device for coupling to a common parallel bus, the bus having coupled thereto an initiator device, the bus having separate data and control lines, and the bus operating according to a sequence of bus phases including information phases to allow for a transfer of information between the initiator device and the target device, the information phases comprising a first information phase allowing the transfer of header information over the bus, a second information phase allowing the transfer of data information over the bus, and a third information phase allowing the transfer of status information over the bus, said target device comprising: (a) means for placing a first control signal on one or more lines indicating the bus is in the first information phase; (b) means responsive to the bus being in the first information phase to receive header information over the bus from the initiator device; (c) means for monitoring the transfer of header information to determine whether one or more error conditions have occurred; (d) means for placing a second control signal on one or more control lines indicating the bus is in the second information phase if said one or more error conditions have not occurred, the bus having transitioned from the first information phase to the second information phase; (e) means responsive to the bus being in the second information phase to receive data information over the bus from the initiator device to the target device; (f) means for placing a third control signal on one or more control lines indicating the bus is in the third information phase, the bus having transitioned to the third information phase from either: (i) said first information phase if said one or more error conditions have occurred, or (ii) said second information phase if said one or more error conditions have not occurred; (g) means responsive to the bus being in the third information phase to transfer status information over said bus from the target device to the initiator device; and (h) means for controlling the means for placing a first control signal, the means for placing a second control signal and the means for placing a third control signal to generate the control signals in response to the determination of the means for monitoring to cause, (i) if said one or more error conditions have not occurred, the information transferred between the target device the initiator device during the information transfer phases always to occur only in the order of header information from the initiator device to the target device, data information from the initiator device to the target device and status information from the target device to the initiator device; and (ii) if said one or more error conditions have occurred, the information transferred between the target device and the initiator device during the information transfer phases always to occur only in the order of header information from the initiator device to the target device and status information from the target device to the initiator device; the order of phase transitions of (i) and (ii) being independent of the configuration of the initiator and the target and independent of the type of information transfer.

Claim 129

A target device for coupling to a common parallel bus, the bus having coupled thereto an initiator device, the bus having separate data and control lines, and the bus operating according to a sequence of bus phases including information phases to allow for a transfer of information between the initiator device and the target device, the information phases comprising a first information phase allowing the transfer of header information over the bus, a second information phase allowing the transfer of data information over the bus, and a third information phase allowing the transfer of status information over the bus, said target device comprising: (a) means for placing a first control signal on one or more lines indicating the bus is in the first information phase; (b) means responsive to the bus being in the first information phase to receive header information over the bus from the initiator device; (c) means for monitoring the transfer of header information to determine whether one or more error conditions have occurred; (d) means for placing a second control signal on one or more control lines indicating the bus is in the second information phase if said one or more error conditions have not occurred, the bus having transitioned from the first information phase to the second information phase; (e) means responsive to the bus being in the second information phase to receive data information over the bus from the initiator device to the target device; (f) means for placing a third control signal on one or more control lines indicating the bus is in the third information phase, the bus having transitioned to the third information phase from either: (i) said first information phase if said one or more error conditions have occurred, or (ii) said second information phase if said one or more error conditions have not occurred; (g) means responsive to the bus being in the third information phase to transfer status information over said bus from the target device to the initiator device; and (h) means for controlling the means for placing a first control signal, the means for placing a second control signal and the means for placing a third control signal to generate the control signals in response to the determination of the means for monitoring to cause, (i) if said one or more error conditions have not occurred, the information transferred between the target device the initiator device during the information transfer phases always to occur only in the order of header information from the initiator device to the target device, data information from the initiator device to the target device and status information from the target device to the initiator device; and (ii) if said one or more error conditions have occurred, the information transferred between the target device and the initiator device during the information transfer phases always to occur only in the order of header information from the initiator device to the target device and status information from the target device to the initiator device; the order of phase transitions of (i) and (ii) being independent of the configuration of the initiator and the target and independent of the type of information transfer.

Claim 130

A target device according to claim 119 wherein the data information comprises command information.