US5287362A
Expired / Lapsed
US
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Mechanism for implementing multiple time-outs
Assignee: Sun Microsystems Inc
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Filing: 1992-05-18
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Granted: 1994-02-15
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Expires: 2012-05-18
Abstract
Abstract A time-out detector for a computer system to record any number of time-out events with a predetermined period. The time-out detector comprises A-counter coupled to a transmission medium for incrementing in response to an initiating event and decrementing in response to a terminating event; B-counter coupled to the transmission medium for incrementing in response to an initiating event and decrementing in response to a terminating event; I-state bit coupled to the A- and B- counters for toggling between logic 0 and logic 1 states at each prescale pulse, wherein the logic 0 state causes the A-counter to increment by 1 count at each initiating event, and the logic 1 state causes the B-counter to increment by 1 count at each initiating event; T-state bit coupled to the A- and B- counters for toggling between logic 0 and logic 1 states, wherein the logic 0 state causes the A-counter to decrement by 1 at each terminating event, and if the contents of said A-counter is then equal to 0, the T-state bit is set to 1. The logic 1 state causes the B-counter to decrement by 1 at each terminating event, and if the contents of said B-counter is then equal to 0, the T-state bit is reset to 0, such that the A-counter records any number of time-out events when the I-state bit is logic 1 and the B-counter records any number of time-out events when the I-state bit is logic 0.
Inventors
- 👤 Bjorn Liencres
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 22:54
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/0703; G06F11/0751; G06F11/0754; G06F11/0757
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
292 words
A time-out detector for a computer system to record any number of time-out events with a predetermined period, each of said time-out events being caused by not detecting an initiating event and terminating event communicated from a transmission medium within said predetermined period after detecting said initiating event, said predetermined period being a multiple of a prescaled period, the beginning and end of said prescaled period being marked by a prescale pulse, said time-out detector comprising: A-counter coupled to said transmission medium for incrementing in response to an initiating event and decrementing in response to a terminating event; B-counter coupled to said transmission medium for incrementing in response to an initiating event and decrementing in response to a terminating event; I-state bit coupled to said A- and B- counters for toggling between logic 0 and logic 1 states at each prescale pulse, said logic 0 state causing said A-counter to increment by 1 count at each initiating event; said logic 1 state causing said B-counter to increment by 1 count at each initiating event; T-state bit coupled to said A- and B- counters for toggling between logic 0 and logic 1 states; said logic 0 state causing said A-counter to decrement by 1 at each terminating event, and if the contents of said A-counter is then equal to 0, said T-state bit being set to 1; said logic 1 state causing said B-counter to decrement by 1 at each terminating event, and if the contents of said B-counter is then equal to 0, said T-state bit being reset to 0, whereby said A-counter records the number of time-out events when said I-state bit is logic 1 and said B-counter records the number of time-out events when said I-state bit is logic 0.
Claim 2
Dependent Claim
292 words
A time-out detector for a computer system to record any number of time-out events with a predetermined period, each of said time-out events being caused by not detecting an initiating event and terminating event communicated from a transmission medium within said predetermined period after detecting said initiating event, said predetermined period being a multiple of a prescaled period, the beginning and end of said prescaled period being marked by a prescale pulse, said time-out detector comprising: A-counter coupled to said transmission medium for incrementing in response to an initiating event and decrementing in response to a terminating event; B-counter coupled to said transmission medium for incrementing in response to an initiating event and decrementing in response to a terminating event; I-state bit coupled to said A- and B- counters for toggling between logic 0 and logic 1 states at each prescale pulse, said logic 0 state causing said A-counter to increment by 1 count at each initiating event; said logic 1 state causing said B-counter to increment by 1 count at each initiating event; T-state bit coupled to said A- and B- counters for toggling between logic 0 and logic 1 states; said logic 0 state causing said A-counter to decrement by 1 at each terminating event, and if the contents of said A-counter is then equal to 0, said T-state bit being set to 1; said logic 1 state causing said B-counter to decrement by 1 at each terminating event, and if the contents of said B-counter is then equal to 0, said T-state bit being reset to 0, whereby said A-counter records the number of time-out events when said I-state bit is logic 1 and said B-counter records the number of time-out events when said I-state bit is logic 0.
Claim 3
Dependent Claim
89 words
A time-out detector according to claim 1, further comprising: C-register coupled to said A- and B-counters for counting sum of said numbers of time-out events recorded by said A- and B- counters, said C-register adding the contents of said B-counter if said contents is not equal to 0 at each prescale pulse, and resetting said B-counter at said prescale pulse; said C-register adding the contents of said A-counter if said contents is not equal to 0 at each prescale pulse, and then resetting said A-counter at said prescale pulse.
Claim 4
Dependent Claim
28 words
A time-out detector according to claim 2, wherein said predetermined period is less than two times said prescaled period and more than said one times said prescaled period.
Claim 5
Dependent Claim
37 words
A time-out detector according to claim 3, wherein said I-state bit is a D-type flip-flop coupled to said A- and B- counters and said T-state bit is a D-type flip-flop coupled to said A- and B- counters.
Claim 6
Dependent Claim
21 words
A time-out detector according to claim 4, wherein said A- and B- counters are bi-directional counters capable of incrementing and decrementing.
Claim 7
Dependent Claim
29 words
A time-out detector according to claim 5, further comprising a prescaler means coupled to said A-counter and B-counter for generating said prescaled pulse after each of said prescaled period.
Claim 8
Independent Claim
237 words
A method of detecting any number of time-out events for a computer system with a predetermined period by using A-counter, B-counter, I-state bit, T-state bit and C-register, each of said time-out events being caused by not detecting an initiating event and terminating event communicated from a transmission medium coupled to said computer system within said predetermined period, the beginning and end of said predetermined period being marked by a prescale pulse, said method comprising: incrementing said A-counter if said I-state equals to 0 at each initiating event; incrementing said B-counter if said I-state bit equals to 1 at each initiating event; decrementing said A-counter if said T-state bit equals to 0 at each terminating event and if said B-counter is then equal to 0, setting said T-state bit to 1; decrementing said B-counter if said T-state bit equals to 1 at each terminating event and if said B-counter is then equal to 0, setting said T-state bit to 0; at each said prescale pulse: setting said I-state bit to 1 if said I-state bit is 0; incrementing said C-register by the contents of said B-counter if said B-counter is not equal to 0, and then resetting said B-counter to 0; resetting said I-state bit to 0 if said I state bit is 1; incrementing said C-register by the contents of said A-counter if said A-counter is not equal to 0, and then resetting said A-counter to 0.
Claim 9
Independent Claim
237 words
A method of detecting any number of time-out events for a computer system with a predetermined period by using A-counter, B-counter, I-state bit, T-state bit and C-register, each of said time-out events being caused by not detecting an initiating event and terminating event communicated from a transmission medium coupled to said computer system within said predetermined period, the beginning and end of said predetermined period being marked by a prescale pulse, said method comprising: incrementing said A-counter if said I-state equals to 0 at each initiating event; incrementing said B-counter if said I-state bit equals to 1 at each initiating event; decrementing said A-counter if said T-state bit equals to 0 at each terminating event and if said B-counter is then equal to 0, setting said T-state bit to 1; decrementing said B-counter if said T-state bit equals to 1 at each terminating event and if said B-counter is then equal to 0, setting said T-state bit to 0; at each said prescale pulse: setting said I-state bit to 1 if said I-state bit is 0; incrementing said C-register by the contents of said B-counter if said B-counter is not equal to 0, and then resetting said B-counter to 0; resetting said I-state bit to 0 if said I state bit is 1; incrementing said C-register by the contents of said A-counter if said A-counter is not equal to 0, and then resetting said A-counter to 0.
Claim 10
Independent Claim
295 words
A method of detecting hardware time-outs for a computer system by recording any number of time-out events with a predetermined period, each of said time-out events being caused by not detecting an initiating event and terminating event communicated from a transmission medium within said predetermined period after detecting said initiating event, said predetermined period being a multiple of a prescaled period, the beginning and end of said prescaled period being marked by a prescale pulse, said method comprising the steps of: incrementing in response to an initiating event and decrementing in response to a terminating event by A-counter coupled to said transmission medium; incrementing in response to an initiating event and decrementing in response to a terminating event by B-counter coupled to said transmission medium; toggling I-state bit coupled to said A- and B- counters between logic 0 and logic 1 states at each prescale pulse, said logic 0 state causing said A-counter to increment by 1 count at each initiating event; said logic 1 state causing said B-counter to increment by 1 count at each initiating event; toggling T-state bit coupled to said A- and B- counters between logic 0 and logic 1 states; said logic 0 state causing said A-counter to decrement by 1 at each terminating event, and if the contents of said A-counter is then equal to 0, said T-state bit being set to 1; said logic 1 state causing said B-counter to decrement by 1 at each terminating event, and if the contents of said B-counter is then equal to 0, said T-state bit being reset to 0, whereby said A-counter records the number of time-out events when said I-state bit is logic 1 and said B-counter records the number of time-out events when said I-state bit is logic 0.
Claim 11
Independent Claim
295 words
A method of detecting hardware time-outs for a computer system by recording any number of time-out events with a predetermined period, each of said time-out events being caused by not detecting an initiating event and terminating event communicated from a transmission medium within said predetermined period after detecting said initiating event, said predetermined period being a multiple of a prescaled period, the beginning and end of said prescaled period being marked by a prescale pulse, said method comprising the steps of: incrementing in response to an initiating event and decrementing in response to a terminating event by A-counter coupled to said transmission medium; incrementing in response to an initiating event and decrementing in response to a terminating event by B-counter coupled to said transmission medium; toggling I-state bit coupled to said A- and B- counters between logic 0 and logic 1 states at each prescale pulse, said logic 0 state causing said A-counter to increment by 1 count at each initiating event; said logic 1 state causing said B-counter to increment by 1 count at each initiating event; toggling T-state bit coupled to said A- and B- counters between logic 0 and logic 1 states; said logic 0 state causing said A-counter to decrement by 1 at each terminating event, and if the contents of said A-counter is then equal to 0, said T-state bit being set to 1; said logic 1 state causing said B-counter to decrement by 1 at each terminating event, and if the contents of said B-counter is then equal to 0, said T-state bit being reset to 0, whereby said A-counter records the number of time-out events when said I-state bit is logic 1 and said B-counter records the number of time-out events when said I-state bit is logic 0.
Claim 12
Dependent Claim
92 words
A method according to claim 8, further comprising the step of: counting sum of said numbers of time-out events recorded by said A- and B- counters by C-register coupled to said A- and B- counters, said C-register adding the contents of said B-counter if said contents is not equal to 0 at each prescale pulse, and resetting said B-counter at said prescale pulse; said C-register adding the contents of said A-counter if said contents is not equal to 0 at each prescale pulse, and then resetting said A-counter at said prescale pulse.
Claim 13
Dependent Claim
27 words
A method according to claim 9, wherein said predetermined period is less than two times said prescaled period and more than said one times said prescaled period.
Claim 14
Dependent Claim
36 words
A method according to claim 10, wherein said I-state bit is a D-type flip-flop coupled to said A- and B- counters and said T-state bit is a D-type flip-flop coupled to said A- and B- counters.
Claim 15
Dependent Claim
20 words
A method according to claim 11, wherein said A- and B- counters are bi-directional counters capable of incrementing and decrementing.
Claim 16
Dependent Claim
30 words
A method according to claim 12, further comprising the step of generating said prescaled pulse after each of said prescaled period a prescaler means coupled to said A-counter and B-counter.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-02-14 | 1997-08-16 | 1998-02-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-02-14 | 2001-08-16 | 2002-02-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-02-14 | 2005-08-16 | 2006-02-15 | $7700.00 | Window Closed / Lapsed |