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US5287353A Expired / Lapsed US ⏱️ 0.0 years remaining

Apparatus for generating and sending a serial data packet for controlling a network of single point I/O devices

Assignee: Schneider Electric USA Inc
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Filing: 1991-12-23
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Granted: 1994-02-15
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Expires: 2011-12-23
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Abstract

Abstract A communication system between a microprocessor based device and a network of a plurality of remote input/output repeater modules that control various input and output devices uses a synchronous serial communications protocol. The microprocessor based device contains a transmitter module for generating a data packet that is sent to the remote input/output repeater modules. The transmitter module controls the clock rate of the network and encodes the data packet with an output data byte for each of the repeater modules. The output byte determines the state of the output devices that may be connected to the remote input/output repeater module coupled to the network.

Inventors

  • 👤 Paul R. Buda
  • 👤 Kelvin Peele

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 20:49
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/16; G06F15/163; G06F15/17; G05; G05B; G05B19/00; G05B19/02; G05B19/04; G05B19/05; G05B19/054; H; H04; H04L; H04L12/00; H04L12/28; H04L12/42; H04L12/423; H04Q; H04Q9/00; H04Q9/14; G05B2219/00; G05B2219/10; G05B2219/11; G05B2219/1116; G05B2219/1131; G05B2219/15; G05B2219/15022; G05B2219/15023

Claims Analysis

Total Claims: 10
Claim 1
Independent Claim 227 words
A transmitter module for transferring data between a microprocessor based device and a network of I/O repeater modules over a synchronous serial communications network, said transmitter module comprising: (A) a buffer register coupled to a data bus in said microprocessor based device, said buffer register for storing data bits generated by said microprocessor based device; (B) an oscillator for generating a clock pulse and a clock rate for said synchronous serial communications network; (C) counter/decoder means for generating a shift/load line based on said clock rate and a data packet length based on the total number of said repeater modules connected to said synchronous serial communications network; (D) a first shift register coupled to said buffer register, said first shift register for storing said data bits coupled from said buffer register and for converting said data bits into a first serial data packet, said conversion at a rate controlled by said shift/load line; (E) a second shift register for receiving said first serial data from said first shift register, said second shift register for inserting an input sync byte and an output sync byte in series with said first serial data packet to produce a second serial data packet synchronized with said shift/load line; and (F) wherein said second serial data packet is coupled to said synchronous serial communications network for transmission to said I/O repeater modules.
Claim 2
Dependent Claim 227 words
A transmitter module for transferring data between a microprocessor based device and a network of I/O repeater modules over a synchronous serial communications network, said transmitter module comprising: (A) a buffer register coupled to a data bus in said microprocessor based device, said buffer register for storing data bits generated by said microprocessor based device; (B) an oscillator for generating a clock pulse and a clock rate for said synchronous serial communications network; (C) counter/decoder means for generating a shift/load line based on said clock rate and a data packet length based on the total number of said repeater modules connected to said synchronous serial communications network; (D) a first shift register coupled to said buffer register, said first shift register for storing said data bits coupled from said buffer register and for converting said data bits into a first serial data packet, said conversion at a rate controlled by said shift/load line; (E) a second shift register for receiving said first serial data from said first shift register, said second shift register for inserting an input sync byte and an output sync byte in series with said first serial data packet to produce a second serial data packet synchronized with said shift/load line; and (F) wherein said second serial data packet is coupled to said synchronous serial communications network for transmission to said I/O repeater modules.
Claim 3
Dependent Claim 31 words
The transmitter module of claim 1 wherein said data bits generated by said microprocessor based device represent status bits for output devices that may be connected to said I/O repeater modules.
Claim 4
Dependent Claim 42 words
The transmitter module of claim 2 wherein said data bits are converted to split-phase binary output bytes by said first shift register, one of said output bytes for each of said I/O repeater modules and included in said first serial data packet.
Claim 5
Dependent Claim 41 words
The transmitter module of claim 3 wherein said second data packet consists of an input sync byte, an output sync byte, and n number of output bytes, where n is the number of said I/O repeater modules connected on said network.
Claim 6
Dependent Claim 34 words
The transmitter module of claim 3 wherein each of said I/O repeater modules connected on said network extracts its respective said output byte from said second data packet for controlling said respective output device.
Claim 7
Dependent Claim 14 words
The transmitter module of claim 1 wherein said device is a programmable logic controller.
Claim 8
Dependent Claim 13 words
The transmitter module of claim 1 wherein said device is a personal computer.
Claim 9
Dependent Claim 28 words
The transmitter module of claim 1 wherein said synchronous serial communications network is a multiconductor wire cable and said second serial data packet is transmitted over said cable.
Claim 10
Dependent Claim 28 words
The transmitter module of claim 1 wherein said synchronous serial communications network is a fiber optic cable and said second serial data packet is transmitted over said cable.

References Cited (Backward Citations)

US4794592A Cited
US4868812A Cited
US4988989A Cited
US5117421A Cited
US5163048A Cited
US5105421A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1997-02-14 1997-08-16 1998-02-15 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2001-02-14 2001-08-16 2002-02-15 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2005-02-14 2005-08-16 2006-02-15 $7700.00 Window Closed / Lapsed

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