Memory device including two-valued/n-valued conversion unit

Claim 2

A memory device comprising: a memory cell array including a plurality of memory cells each for storing an n-valued (n is an integer of 3 or larger) digital data; means for converting a binary digital data applied thereto into an n-valued digital data using a plurality of logic operating circuits when the binary digital data is written into said memory cell array; and means for converting an n-valued digital data into a binary digital data using a plurality of logic operating circuits when the n-valued digital data is read out from said memory cell array.

Claim 3

A memory device according to claim 1, wherein said means for converting a binary digital data into an n-valued digital data include at least a decoder and an encoder.

Claim 4

A memory device according to claim 2, wherein for one digital 4-valued or quaternary signal applied to one memory cell, said decoder comprises two inverters each receiving an input binary logic signal and three first AND logic circuits each receiving one of said input binary logic signals, two of said first AND circuits being connected to outputs of said inverters respectively, and wherein said encoder comprises two second AND logic circuits each receiving an quaternary constant datum except the highest state datum and the lowest state datum and connected to one of said first AND circuits, and an OR circuit connected to outputs of said second AND circuits and one first AND circuit, an quaternary logic signal being output by said OR circuit.

Claim 5

A memory device according to claim 2, wherein for two digital 3-valued or ternary signals applied to two memory cells, said decoder comprises three inverters each receiving an input binary logic signal and six first AND logic circuits each receiving at least one of said input binary logic signals, some of said first AND circuits being connected to outputs of said inverters respectively, and said encoder comprises two first OR circuits each connected to two of said first AND circuits, two second AND logic circuits each receiving a middle state constant data and connected to said first OR circuits, and second OR circuits connected respectively to outputs of said second AND circuits and two first AND circuits, two ternary logic signals being output respectively by said second OR circuits.

Claim 6

A memory device according to claim 3, wherein said means for converting an n-valued digital data into a binary digital data include at least a decoder and an encoder.

Claim 7

A memory device according to claim 5, wherein said decoder comprises a plurality of equivalent circuits each determining whether an n-valued digital data read out of said memory cell array is equivalent to a constant n-valued digital data or not thereby to output a state 1 signal to said encoder if the n-valued data equals the constant data.

Claim 8

A memory device according to claim 6, wherein for one quaternary digital signal read out of one memory cell, said decoder comprises three equivalent circuits connected in parallel to an input receiving a quaternary digital data, and said encoder comprises two OR circuits each connected to two of said equivalent circuits, two binary digital data being output by said OR circuits.

Claim 9

A memory device according to claim 6, wherein for two ternary digital signals read out of two memory cells, said decoder comprises two sets of three equivalent circuits connected in parallel to an input receiving one of said two ternary digital data, and said encoder comprises nine AND circuits each connected to two of said equivalent circuits, three binary digital data being output by said AND circuits.

Claim 10

A memory device according to claim 1, wherein said means for converting a binary digital data into an n-valued digital data and said means for converting an n-valued digital data into a binary digital data are composed of a bidirectional n-valued/binary data conversion circuit and a bidirectional amplifier coupled between said memory cell array and said bidirectional n-valued/binary data conversion circuit.

Claim 11

A memory device according to claim 9, wherein said bidirectional n-valued/binary data conversion circuit is a bidirectional binary/quaternary conversion circuit for converting a binary digital data into a quaternary digital data and vice versa.

Claim 12

A memory device according to claim 9, wherein said bidirectional n-valued/binary data conversion circuit is a bidirectional binary/ternary conversion circuit for converting a binary digital data into a ternary digital data and vice versa.

Claim 13

A memory device comprising: a memory cell array including a plurality of memory cells each for storing a digital n-valued (n is integer of 3 or larger) datum; means for converting a binary digital data applied thereto into an n-valued digital data using a plurality of logic operating circuits when the binary digital data is written into said memory cell array; means for converting an n-valued digital data into a binary digital data using a plurality of logic operating circuits when the n-valued digital data is read out from said memory cell array; and means for decoding an n-valued logic address applied thereto and for outputting a signal decoded from the n-valued logic address to said memory cell array.

Claim 14

A memory device comprising: a memory cell array including a plurality of memory cells each for storing a digital n-valued (n is integer of 3 or larger) datum; means for converting a binary digital data applied thereto into an n-valued digital data using a plurality of logic operating circuits when the binary digital data is written into said memory cell array; means for converting an n-valued digital data into a binary digital data using a plurality of logic operating circuits when the n-valued digital data is read out from said memory cell array; and means for decoding an n-valued logic address applied thereto and for outputting a signal decoded from the n-valued logic address to said memory cell array.

Claim 15

A memory device according to claim 12, wherein said means for converting a binary digital data into an n-valued digital data include at least a decoder and an encoder.

Claim 16

A memory device according to claim 13, wherein for one digital 4-valued or quaternary signal applied to one memory cell, said decoder comprises two inverters each receiving an input binary logic signal and three first AND logic circuits each receiving one of said input binary logic signals, two of said first AND circuits being connected to outputs of said inverters respectively, and wherein said encoder comprises two second AND logic circuits each receiving an quaternary constant data except the highest state datum and the lowest state datum and connected to one of said first AND circuits, and an OR circuit connected to outputs of said second AND circuits and one first AND circuit, an quaternary logic signal being output by said OR circuit.

Claim 17

A memory device according to claim 13, wherein for two digital 3-valued or ternary signals applied to two memory cells, and said decoder comprises three inverters each receiving an input binary logic signal and six first AND logic circuits each receiving at least one of said input binary logic signals, some of said first AND circuits being connected to outputs of said inverters respectively, and said encoder comprises two first OR circuits each connected to two of said first AND circuits, two second AND logic circuits each receiving a middle state constant data and connected to said first OR circuits, and second OR circuits connected respectively to outputs of said second AND circuits and two first AND circuits, two ternary logic signals being output respectively by said second OR circuits.

Claim 18

A memory device according to claim 12, wherein said means for converting an n-valued digital data into a binary digital data include at least a decoder and an encoder.

Claim 19

A memory device according to claim 16, wherein said decoder comprises a plurality of equivalent circuits each determining whether an n-valued digital data read out of said memory cell array is equivalent to a constant n-valued digital data or not thereby to output a state 1 signal to said encoder if the n-valued data equals the constant data.

Claim 20

A memory device according to claim 16, wherein for one quaternary digital signal read out of one memory cell, said decoder comprises three equivalent circuits connected in parallel to an input receiving a quaternary digital data, and said encoder comprises two OR circuits each connected to two of said equivalent circuits, two binary digital data being output by said OR circuits.

Claim 21

A memory device according to claim 16, wherein for two ternary digital signals read out of two memory cells, said decoder comprises two sets of three equivalent circuits connected in parallel to an input receiving one of said two ternary digital data, and said encoder comprises nine AND circuits each connected to two of said equivalent circuits, three binary digital data being output by said AND circuits.

Claim 22

A memory device according to claim 12, wherein said means for converting a binary digital data into an n-valued digital data and said means for converting an n-valued digital data into a binary digital data are composed of a bidirectional n-valued/binary data conversion circuit and a bidirectional amplifier coupled between said memory cell array and said bidirectional n-valued/binary data conversion circuit, and said decoding means includes m address inputs, m groups of n equivalent circuits each connected to the respective address input, and a binary decoder connected to said all equivalent circuits and said memory cell array.

Claim 23

A memory device according to claim 20, wherein said bidirectional n/valued/binary data conversion circuit is a bidirectional binary/quaternary conversion circuit for converting a binary digital data into a quaternary digital data and vice versa.

Claim 24

A memory device according to claim 20, wherein said bidirectional n-valued/binary data conversion circuit is a bidirectional binary/ternary conversion circuit for converting a binary digital data into a ternary digital data and vice versa.

Claim 25

A memory device according to claim 20, wherein said decoding means further includes a logic converting circuit connected to said address inputs for converting a binary address from the outside into an n-valued address and supplying the n-valued address to said address inputs.

Claim 26

A memory device comprising: a memory cell array including a plurality of memory cells each for storing a digital n-valued (n is an integer of 3 or larger) data; means for converting a binary digital data applied thereto into an n-valued digital data using a plurality of logic operating circuits when the binary digital data is written into said memory cell array; and means for converting an n-valued digital data into a binary digital data using a plurality of logic operating circuits when the n-valued digital data is read out from said memory cell array, said means for converting a binary digital data into an n-valued digital data and said means for converting an n-valued digital data into a binary digital data being composed of a bidirectional n-valued/binary data conversion circuit and a bidirectional amplifier coupled between said memory cell array and said bidirectional n-valued/binary data conversion circuits.

Claim 27

A memory device comprising: a memory cell array including a plurality of memory cells each for storing a digital n-valued (n is an integer of 3 or larger) data; means for converting a binary digital data applied thereto into an n-valued digital data using a plurality of logic operating circuits when the binary digital data is written into said memory cell array; and means for converting an n-valued digital data into a binary digital data using a plurality of logic operating circuits when the n-valued digital data is read out from said memory cell array, said means for converting a binary digital data into an n-valued digital data and said means for converting an n-valued digital data into a binary digital data being composed of a bidirectional n-valued/binary data conversion circuit and a bidirectional amplifier coupled between said memory cell array and said bidirectional n-valued/binary data conversion circuits.

Claim 28

A memory device according to claim 24, wherein said means for converting a binary digital data into an n-valued digital data include at least a decoder and an encoder.

Claim 29

A memory device according to claim 24, wherein for one digital 4-valued or quaternary signal applied to one memory cell, said decoder comprises two inverters each receiving an input binary logic signal and three first AND logic circuits each receiving one of said input binary logic signals, two of said first AND circuits being connected to outputs of said inverters respectively, and wherein said encoder comprises two second AND logic circuits each receiving an quaternary constant datum except the highest state datum and the lowest state datum and connected to one of said first AND circuits, and an OR circuit connected to outputs of said second AND circuits and one first AND circuit, an quaternary logic signal being output by said OR circuit.

Claim 30

A memory device according to claim 25, wherein for two digital 3-valued or ternary signals applied to two memory cells, said decoder comprises three inverters each receiving an input binary logic signal and six first AND logic circuits each receiving at least one of said input binary logic signals, some of said first AND circuits being connected to outputs of said inverters respectively, and said encoder comprises two first OR circuits each connected to two of said first AND circuits, two second AND logic circuits each receiving a middle state constant data and connected to said first OR circuits, and second OR circuits connected respectively to outputs of said second AND circuits and two first AND circuits, two ternary logic signals being output respectively by said second OR circuits.

Claim 31

A memory device according to claim 24, wherein said means for converting an n-valued digital data into a binary digital data include at least a decoder and an encoder.

Claim 32

A memory device according to claim 28, wherein said decoder comprises a plurality of equivalent circuits each determining whether an n-valued digital data read out of said memory cell array is equivalent to a constant n-valued digital data or not thereby to output a state 1 signal to said encoder if the n-valued data equals the constant data.

Claim 33

A memory device according to claim 29, wherein for one quaternary digital signal read out of one memory cell, said decoder comprises three equivalent circuits connected in parallel to an input receiving a quaternary digital data, and said encoder comprises two OR circuits each connected to two of said equivalent circuits, two binary digital data being output by said OR circuits.

Claim 34

A memory device according to claim 29, wherein for two ternary digital signals read out of two memory cells, said decoder comprises two sets of three equivalent circuits connected in parallel to an input receiving one of said two ternary digital data, and said encoder comprises nine AND circuits each connected to two of said equivalent circuits, three binary digital data being output by said AND circuits.

Claim 35

A memory device according to claim 24, wherein said bidirectional n-valued/binary data conversion circuit is a bidirectional binary/quaternary conversion circuit for converting a binary digital data into a quaternary digital data and vice versa.

Claim 36

A memory device according to claim 24, wherein said bidirectional n-valued/binary data conversion circuit is a bidirectional binary/ternary conversion circuit for converting a binary digital data into a ternary digital data and vice versa.

Claim 37

A memory device according to claim 24, wherein said device further comprises means for decoding an n-valued logic address applied thereto and for outputting a signal decoded from the n-valued logic address to aid memory cell array.

Claim 38

A memory device according to claim 34, wherein said decoding means include m address inputs, m groups of n equivalent circuits each connected to the respective address input, and a binary decoder connected to said all equivalent circuits and said memory cell array.