US5286670A
Expired / Lapsed
US
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Method of manufacturing a semiconductor device having buried elements with electrical characteristic
Assignee: Electronics and Telecommunications Research Institute
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Filing: 1992-05-08
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Granted: 1994-02-15
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Expires: 2012-05-08
Abstract
Abstract There are disclosed a semiconductor device having electrical elements buried a SOI substrate and a manufacturing method thereof, the manufacturing method of the invention comprising the steps of: (a) forming a first isolating insulator layer at a seed wafer by using an isolation mask, depositing a second isolating insulator layer overlying the first isolating insulator layer and the seed wafer, and defining contact holes by using a contact mask to form contacts on the seed wafer; (b) depositing a first polysilicon layer on the second isolating insulator layer and the contacts and doping an impurity into the first polysilicon layer; (c) patterning the first polysilicon layer to define an electrical element, depositing an insulating layer around the electrical element, and forming a second polysilicon layer overlying the second isolating insulator layer and the insulating layer; (d) doping an impurity into the second polysilicon layer for connecting with a handling wafer, and polishing the second polysilicon layer thus doped to form a mirror surface; (e) depositing an insulating layer for connection on the handling wafer, and performing a thermal process to bond the handling wafer and the mirror surface through the insulating layer for connection; and (f) polishing the seed wafer until the first isolating insulator layer as a polishing stopper is exposed, to form the SOI substrate having an active region where a device is formed, by the invention the efficiency of chip area can be promoted.
Inventors
- 👤 Sang-Won Kang
- 👤 Hyun-Kyu Yu
- 👤 Won-Gu Kang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 03:32
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/40; H10D1/47; H10D1/60; H10D1/68; H10P; H10P90/00; H10P90/19; H10P90/1904; H10P90/1906; H10P90/1912; H10P90/1914; H10W; H10W10/00; H10W10/10; H10W10/181; H10W20/00; H10W20/01; H10W20/021; H10W20/20; Y; Y10; Y10S; Y10S148/00; Y10S148/012; Y10S148/135
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
219 words
A method for manufacturing a semiconductor device having buried elements with electrical characteristic in a SOI substrate comprising the steps of: (a) forming a first isolating insulator layer at a seed wafer by using an isolation mask, depositing a second isolating insulator layer overlying the first isolating insulator layer and the seed wafer, and defining contact holes by using a contact mask to form contacts on the seed wafer; (b) depositing a first polysilicon layer on the second isolating insulator layer and the contacts and doping an impurity into the first polysilicon layer; (c) patterning the first polysilicon layer to define an electrical element, depositing an insulating layer around the electrical element, and forming a second polysilicon layer overlying the second isolating insulator layer and the insulating layer; (d) doping an impurity into the second polysilicon layer for connecting with a handling wafer, and polishing the second polysilicon layer thus doped to form a mirror surface; (e) depositing an insulating layer for connection on the handling wafer, and performing a thermal process to bond the handling wafer and the mirror surface through the insulating layer for connection; and (f) polishing the seed wafer until the first isolating insulator layer as a polishing stopper is exposed, to form the SOI substrate having an active region where a device is formed.
Claim 2
Independent Claim
219 words
A method for manufacturing a semiconductor device having buried elements with electrical characteristic in a SOI substrate comprising the steps of: (a) forming a first isolating insulator layer at a seed wafer by using an isolation mask, depositing a second isolating insulator layer overlying the first isolating insulator layer and the seed wafer, and defining contact holes by using a contact mask to form contacts on the seed wafer; (b) depositing a first polysilicon layer on the second isolating insulator layer and the contacts and doping an impurity into the first polysilicon layer; (c) patterning the first polysilicon layer to define an electrical element, depositing an insulating layer around the electrical element, and forming a second polysilicon layer overlying the second isolating insulator layer and the insulating layer; (d) doping an impurity into the second polysilicon layer for connecting with a handling wafer, and polishing the second polysilicon layer thus doped to form a mirror surface; (e) depositing an insulating layer for connection on the handling wafer, and performing a thermal process to bond the handling wafer and the mirror surface through the insulating layer for connection; and (f) polishing the seed wafer until the first isolating insulator layer as a polishing stopper is exposed, to form the SOI substrate having an active region where a device is formed.
Claim 3
Dependent Claim
21 words
The method according to claim 1 wherein the electrical element is formed vertically under the active region of the seed wafer.
Claim 4
Dependent Claim
106 words
The method according to claim 1 wherein the first isolating insulator layer is formed between the active regions of the SOI substrate, wherein the Second isolating insulator layer is formed between the active region and the electrical element, wherein the insulating layer is formed between the electrical element and the second polysilicon layer, and wherein the insulating layer for connection is formed between the second polysilicon layer and the handling wafer, whereby the active region and the electrical element are vertically located for electrical isolation from each other, and the second polysilicon layer and the handling wafer are vertically located for electrical isolating from each other.
Claim 5
Dependent Claim
83 words
The method according to claim 1 wherein the insulating layer between the electrical element and the second polysilicon is used as a capacitor dielectric layer, a first contact between the active region and the electrical element is used as a substrate contact, a second contact on the active region is used as a node contact, and a third contact on the second polysilicon layer is used as a plate contact, whereby the electrical element buried in the SOI substrate serves as a capacitor.
Claim 6
Dependent Claim
19 words
The method according to claim 1 wherein the electrical element serves as a resistive line for electrical connecting devices.
Claim 7
Dependent Claim
25 words
The method according to claim 1 wherein the electrical element serves as an interconnector for electrical connecting devices to be formed in the active regions.
Claim 8
Dependent Claim
21 words
The method according to claim 1 wherein the first polysilicon layer is for one of a refractory metal, polycide, and Silicide.
Claim 9
Dependent Claim
26 words
The method according to claim 6 wherein a plurality of laminated construction composed of the resistive line and the interconnector are formed in the SOI substrate.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-02-14 | 1997-08-16 | 1998-02-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-02-14 | 2001-08-16 | 2002-02-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-02-14 | 2005-08-16 | 2006-02-15 | $7700.00 | Window Closed / Lapsed |