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US5285451A
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Failure-tolerant mass storage system
Assignee: EMC Corp
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Filing: 1992-07-15
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Granted: 1994-02-08
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Expires: 2012-07-15
Abstract
Abstract A mass memory system for digital computers is disclosed. The system has a plurality of disk drives coupled to a plurality of small buffers. An Error Correction Controller is coupled to a plurality of X-bar switches, the X-bar switches being connected between each disk drive and its buffers. Data is read from and written to the disk drives in parallel and error correction is also performed in parallel. The X-bar switches are used to couple and decouple functional and nonfunctional disk drives to the system as necessary. Likewise, the buffers can be disconnected from the system should they fail. The parallel architecture, combined with a Reed-Solomon error detection and correction scheme and X-bar switches allows the system to tolerate and correct any two failed drives, allowing for high fault-tolerance operation.
Inventors
- 👤 Larry P. Henson
- 👤 Kumar Gajjar
- 👤 David T. Powers
- 👤 Thomas E. Idleman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 15:21
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1076; G06F11/16; G06F11/1666; G06F11/20; G06F11/2002; G06F11/2007; G06F11/201; G06F11/2053; G06F11/2094; G11; G11B; G11B20/00; G11B20/10; G11B20/18; G11B20/1833; G06F11/0703; G06F11/0751; G06F11/0754; G06F11/0757; G06F11/2089; G06F2211/00; G06F2211/10; G06F2211/1002; G06F2211/1057
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
146 words
An interface for connecting to a plurality of memory storage means comprising: a plurality of output buffer means coupled to a first bus; a plurality of cross-bar switches, each individual cross-bar switch being coupled to only a single one of said individual memory storage means by a bi-directional bus means and to an individual output buffer means by a bi-directional bus means, all of said cross-bar switches being coupled to each other each cross-bar switch providing a pair of data paths, a first one of said data paths having means for delaying data; and control means coupled to each cross-bar switch for controlling the cross-bar switches to allow data both to flow from any selected output buffer means to any selected memory storage means and to flow from any selected memory storage means to any selected output buffer means, and to select between said data paths.
Claim 2
Dependent Claim
146 words
An interface for connecting to a plurality of memory storage means comprising: a plurality of output buffer means coupled to a first bus; a plurality of cross-bar switches, each individual cross-bar switch being coupled to only a single one of said individual memory storage means by a bi-directional bus means and to an individual output buffer means by a bi-directional bus means, all of said cross-bar switches being coupled to each other each cross-bar switch providing a pair of data paths, a first one of said data paths having means for delaying data; and control means coupled to each cross-bar switch for controlling the cross-bar switches to allow data both to flow from any selected output buffer means to any selected memory storage means and to flow from any selected memory storage means to any selected output buffer means, and to select between said data paths.
Claim 3
Independent Claim
170 words
A system for transferring data from a computer to a plurality of data storage means, comprising: a plurality of buffer means, each buffer means being coupled by a bus means to the computer; a plurality of switching means, each switching means being coupled both to a data storage means by a bi-directional bus means and to a buffer means by a bi-directional bus means, each switching means providing a pair of data paths, a first one of said data paths having a means for delaying data; error detection and correction means, coupled individually to each switching means by a bus means, for detecting and correcting errors in the data as the data is transmitted in parallel both from the buffer means to the data storage means through the switching means and from the data storage means to the buffer means through the switching means; and control means, coupled to the error detection and correction means, for controlling the error detection and correction means and selecting one of said data paths.
Claim 4
Independent Claim
170 words
A system for transferring data from a computer to a plurality of data storage means, comprising: a plurality of buffer means, each buffer means being coupled by a bus means to the computer; a plurality of switching means, each switching means being coupled both to a data storage means by a bi-directional bus means and to a buffer means by a bi-directional bus means, each switching means providing a pair of data paths, a first one of said data paths having a means for delaying data; error detection and correction means, coupled individually to each switching means by a bus means, for detecting and correcting errors in the data as the data is transmitted in parallel both from the buffer means to the data storage means through the switching means and from the data storage means to the buffer means through the switching means; and control means, coupled to the error detection and correction means, for controlling the error detection and correction means and selecting one of said data paths.
Claim 5
Dependent Claim
61 words
The system of claim 2 wherein the control means is additionally coupled to the data storage means and the buffer means, the control means receiving from the data storage means and the buffer means the locations of failed buffer means and failed data storage means, the control means electronically decoupling the failed buffer means and/or data storage means from the system.
Claim 6
Dependent Claim
38 words
The system of claim 2 wherein the error detection and correction means uses a Reed-Solomon error correction code to detect and correct the errors in the data received from the data buffer means and the data storage means.
Claim 7
Dependent Claim
44 words
The system of claim 2 further comprising a plurality of switches coupling said buffer means to said data storage means and control means coupled to said switches for electronically removing from the system any data storage means and buffer means which transmits erroneous data.
Claim 8
Dependent Claim
15 words
The interface of claim 1 wherein said means for delaying comprises at least one register.
Claim 9
Dependent Claim
17 words
The interface of claim 1 wherein said control means includes a multiplexer coupled to said data paths.
Claim 10
Dependent Claim
41 words
The interface of claim 1 further comprising a plurality of word assembler means, each coupled between one of said buffer means and one of said cross-bar switches, for converting from an N bit path to an M times N bit path.
Claim 11
Dependent Claim
31 words
The system of claim 2 wherein said first path is coupled to said error detection and correction means and delays data for error checking by said error detection and correction means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-02-07 | 1997-08-09 | 1998-02-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-02-07 | 2001-08-09 | 2002-02-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-02-07 | 2005-08-09 | 2006-02-08 | $7700.00 | Window Closed / Lapsed |