Semiconductor memory having transistors which drive data lines in accordance with values of write data and column select signal

Claim 2

A semiconductor memory comprising: a plurality of columns each including a plurality of memory cells and a logic circuit; a column select line, associated with each of said plurality of columns, which delivers a column select signal for selecting one of said columns; and a plurality of data lines each corresponding to a respective column, wherein each of said plurality of data lines is selectively connected to an input/output node of one of the memory cells included in a corresponding one of said plurality of columns when the corresponding column is selected by said column select signal, and wherein said logic circuit includes a first transistor for driving the corresponding data line to a "high" level, indicative of a logic "high" level write data written into a selected memory cell of the corresponding column, during a write mode, upon the corresponding column being selected by said column select signal, and a second transistor for driving the corresponding data line to a "low" level, indicative of a logic "low" level write data written into said memory cell, upon the corresponding column being selected by said column select signal, said first and second transistors of each said corresponding column functioning as bit loads of corresponding ones of said data lines when data is read out from said memory cell included in the corresponding column.

Claim 3

A semiconductor memory comprising: a plurality of columns each including a plurality of memory cells and data lines; and column select lines, which deliver a column select signal for selecting one of said columns, coupled to each of said columns, wherein each of said plurality of data lines is selectively connected to an input/output node of a memory cell included in a corresponding column upon the corresponding column being selected by said column select signal, and wherein each of said columns further includes: (i) a driver circuit which drives corresponding ones of said data lines to a level in accordance with a value of write data to be written into a selected memory cell upon the corresponding column being selected by said column select signal, during a write mode; and (ii) transistors which function as bit loads when stored data is read out from the selected memory cell included in the corresponding column and which have their ON/OFF states controlled in accordance with the value of the write data when the data is written.

Claim 4

A semiconductor memory comprising: a plurality of columns each including a plurality of memory cells and data lines; and column select lines, which deliver a column select signal for selecting one of said columns, coupled to each of said columns, wherein each of said plurality of data lines is selectively connected to an input/output node of a memory cell included in a corresponding column upon the corresponding column being selected by said column select signal, and wherein each of said columns further includes: (i) a driver circuit which drives corresponding ones of said data lines to a level in accordance with a value of write data to be written into a selected memory cell upon the corresponding column being selected by said column select signal, during a write mode; and (ii) transistors which function as bit loads when stored data is read out from the selected memory cell included in the corresponding column and which have their ON/OFF states controlled in accordance with the value of the write data when the data is written.

Claim 5

A semiconductor memory comprising: a plurality of columns each including a plurality of memory cells and data lines; column select lines, which deliver a column select signal for selecting one of said columns, coupled to each of said columns; and write enable lines which deliver a write enable signal designating a write operation to each of said columns, wherein each of said plurality of data lines is selectively connected to an input/output node of one of the memory cells included in a corresponding one of said plurality of columns when the corresponding column is selected by said column select signal, and wherein each of said columns further includes: a write driver including first MOSFETs respectively coupled to data lines included in the corresponding column and operating, in accordance with said write enable signal for designating a write operation and a value of write data, so as to be in an ON state and pull up a corresponding data line at operating times other than the write operation as designated by said enable signal, to maintain the ON state and pull up the corresponding data line when driving the corresponding data line to a "high" level when the write operation is designated by said enable signal, and to switch into an OFF state when driving the corresponding data line to a "low" level when the write operation is designated by said enable signal; and second MOSFETs, respectively coupled to data lines included in the corresponding column and operating, in accordance with said write enable signal, said column select signal and the value of the write data, so as to be controllably set into an OFF state at operating times other than the write operation, as designated by said write enable signal, and to switch into an ON state and lower a potential level of the corresponding data line to that of the "low" level when driving the data line to the "low" level when the write operation is designated by said write enable signal and the corresponding column is selected by said column select signal.

Claim 6

A semiconductor memory comprising: a plurality of columns each including a plurality of memory cells and data lines; column select lines, which deliver a column select signal for selecting one of said columns, coupled to each of said columns; and write enable lines which deliver a write enable signal designating a write operation to each of said columns, wherein each of said plurality of data lines is selectively connected to an input/output node of one of the memory cells included in a corresponding one of said plurality of columns when the corresponding column is selected by said column select signal, and wherein each of said columns further includes: a write driver including first MOSFETs respectively coupled to data lines included in the corresponding column and operating, in accordance with said write enable signal for designating a write operation and a value of write data, so as to be in an ON state and pull up a corresponding data line at operating times other than the write operation as designated by said enable signal, to maintain the ON state and pull up the corresponding data line when driving the corresponding data line to a "high" level when the write operation is designated by said enable signal, and to switch into an OFF state when driving the corresponding data line to a "low" level when the write operation is designated by said enable signal; and second MOSFETs, respectively coupled to data lines included in the corresponding column and operating, in accordance with said write enable signal, said column select signal and the value of the write data, so as to be controllably set into an OFF state at operating times other than the write operation, as designated by said write enable signal, and to switch into an ON state and lower a potential level of the corresponding data line to that of the "low" level when driving the data line to the "low" level when the write operation is designated by said write enable signal and the corresponding column is selected by said column select signal.

Claim 7

A semiconductor memory as defined claim 3, wherein each column consists of a pair of complementary data lines including a noninverting data line associated with a logic level indicative of stored data of said memory cell, and an inverting data line, associated with a logic level indicative of the logic complement of the stored data of said memory cell selectively coupled thereto, said noninverting and inverting data lines are connected to corresponding ones of a pair of input/output nodes of said memory cell, wherein said first MOSFETs consist of two PMOSFETs which are disposed so as to correspond respectively to said noninverting data line and said inverting data line, and wherein the ON/OFF states of said PMOSFET disposed in correspondence with said noninverting data line are controlled using inverted data as a gate signal thereof when the write operation is designated by said write enable signal, the inverted data being obtained by inverting the write data, while the ON/OFF states of said PMOSFET disposed in correspondence with said inverting data line are controlled using the write data as a gate signal thereof when the write operation is designated by said write enable signal.

Claim 8

A semiconductor memory as defined in claim 3, wherein each of said columns further includes a column selection deciding circuit which produces a low potential in a case in which the corresponding column is selected by said column select signal, and wherein in the case in which the data line is driven to the low level, one of said second MOSFETs of a column is switched into the ON state to connect the data line with said column selection deciding circuit, thereby to change a potential of the data line to the low potential produced by said column selection deciding circuit.

Claim 9

A semiconductor memory comprising: a plurality of columns each including a plurality of memory cells and data lines; column select lines, which deliver a column select signal for selecting one of said columns, coupled to each of said columns; and write enable lines which deliver a write enable signal designating a write operation to each of said columns, wherein each of said plurality of data lines is selectively connected to an input/output node of one of the memory cells included in a corresponding one of said plurality of columns when the corresponding column is selected by said column select signal, and wherein each of said columns further includes: a write driver including first MOSFETs respectively coupled to data lines included in the corresponding column and operating, in accordance with said write enable signal for designating a write operation and a value of write data, so as to be in an ON state and pull up the corresponding data line at operating times other than the write operation as designated by said enable signal, to maintain the ON state and pull up the corresponding data line when driving the corresponding data line to a "high" level when the write operation is designated by said enable signal, and to switch into an OFF state when driving the corresponding data line to a "low" level when the write operation is designated by said enable signal, second MOSFETs, respectively coupled to data lines included in the corresponding column and operating in accordance with said write enable signal, said column select signal and the value of the write data, so as to be controllably set into an OFF state at operating times other than the write operation as designated by said write enable signal, and to switch into an ON state and lower a potential level of the corresponding data line to that of the "low" level when driving the data line to the "low" level when the write operation is designated by said write enable signal and the corresponding column is selected by said column select signal; and read lines which are used for reading out stored data from a selected memory cell of a column, a reading gate circuit which changes into an ON state to connect said data lines of a column with said read lines in a case in which a memory cell of a corresponding column is read out, and a write mode detection circuit which brings said reading gate circuit into an OFF state, unconditionally, in the write mode.

Claim 10

A semiconductor memory comprising: a plurality of columns each including a plurality of memory cells and data lines; column select lines, which deliver a column select signal for selecting one of said columns, coupled to each of said columns; and write enable lines which deliver a write enable signal designating a write operation to each of said columns, wherein each of said plurality of data lines is selectively connected to an input/output node of one of the memory cells included in a corresponding one of said plurality of columns when the corresponding column is selected by said column select signal, and wherein each of said columns further includes: a write driver including first MOSFETs respectively coupled to data lines included in the corresponding column and operating, in accordance with said write enable signal for designating a write operation and a value of write data, so as to be in an ON state and pull up the corresponding data line at operating times other than the write operation as designated by said enable signal, to maintain the ON state and pull up the corresponding data line when driving the corresponding data line to a "high" level when the write operation is designated by said enable signal, and to switch into an OFF state when driving the corresponding data line to a "low" level when the write operation is designated by said enable signal, second MOSFETs, respectively coupled to data lines included in the corresponding column and operating in accordance with said write enable signal, said column select signal and the value of the write data, so as to be controllably set into an OFF state at operating times other than the write operation as designated by said write enable signal, and to switch into an ON state and lower a potential level of the corresponding data line to that of the "low" level when driving the data line to the "low" level when the write operation is designated by said write enable signal and the corresponding column is selected by said column select signal; and read lines which are used for reading out stored data from a selected memory cell of a column, a reading gate circuit which changes into an ON state to connect said data lines of a column with said read lines in a case in which a memory cell of a corresponding column is read out, and a write mode detection circuit which brings said reading gate circuit into an OFF state, unconditionally, in the write mode.

Claim 11

A semiconductor memory according to claim 1 provided in a microprocessor.

Claim 12

A semiconductor memory according to claim 1 provided in a gate array.

Claim 13

A semiconductor memory according to claim 2 provided in a microprocessor.

Claim 14

A semiconductor memory according to claim 2 provided in a gate array.

Claim 15

A data writing method for a semiconductor memory in which the semiconductor memory includes: a plurality of columns each including a plurality of memory cells and a transistor which is in ON state and functions as a bit load of a data line associated therewith when data is read out from a selected memory cell, included in the corresponding column; a column select line, associated with each of said plurality of columns, which delivers a column select signal for selecting one of said columns; and a plurality of data lines each of which corresponds to a respective column and is selectively connected to an input/output node of respective ones of memory cells included in a corresponding column when the corresponding column is selected by said column select signal, said method comprising the steps wherein: data to be stored is written into the memory cell by driving the corresponding data line to a "high" or "low" level in accordance with a value of the input data to-be-written, and in a case in which said data lines are driven to the low level, said transistor is brought into an OFF state in accordance with the value of input data to-be-written and the column select signal.

Claim 16

A data writing method for a semiconductor memory in which the semiconductor memory includes: a plurality of columns each including a plurality of memory cells and a transistor which is in ON state and functions as a bit load of a data line associated therewith when data is read out from a selected memory cell, included in the corresponding column; a column select line, associated with each of said plurality of columns, which delivers a column select signal for selecting one of said columns; and a plurality of data lines each of which corresponds to a respective column and is selectively connected to an input/output node of respective ones of memory cells included in a corresponding column when the corresponding column is selected by said column select signal, said method comprising the steps wherein: data to be stored is written into the memory cell by driving the corresponding data line to a "high" or "low" level in accordance with a value of the input data to-be-written, and in a case in which said data lines are driven to the low level, said transistor is brought into an OFF state in accordance with the value of input data to-be-written and the column select signal.

Claim 17

A data writing method for a semiconductor memory in which the semiconductor memory includes: a plurality of columns each including a plurality of memory cells and a transistor which is in ON state and functions as a bit load of a data line associated therewith when data is read out from a selected memory cell, included in the corresponding column; column select lines, which deliver a column select signal for selecting one of said columns, provided to each of said columns; and a plurality of data lines each pair of which corresponding to a respective column and being selectively connected to input/output nodes of respective ones of memory cells included in the corresponding column in accordance with selection of the corresponding column by said column select signal, said method comprising the steps wherein: data to be stored is written into the memory cell by driving the corresponding pair of data lines to a "high" or "low" level in accordance with the value of the input data to-be-written and said column select signal, and each said data line is driven to the high level by the use of a corresponding said transistor, coupled thereto, and each said transistor functioning as said bit load in a case in which said data lines are to be driven to the high level.

Claim 18

A data writing method for a semiconductor memory in which the semiconductor memory includes: a plurality of columns each including a plurality of memory cells and a transistor which is in ON state and functions as a bit load of a data line associated therewith when data is read out from a selected memory cell, included in the corresponding column; column select lines, which deliver a column select signal for selecting one of said columns, provided to each of said columns; and a plurality of data lines each pair of which corresponding to a respective column and being selectively connected to input/output nodes of respective ones of memory cells included in the corresponding column in accordance with selection of the corresponding column by said column select signal, said method comprising the steps wherein: data to be stored is written into the memory cell by driving the corresponding pair of data lines to a "high" or "low" level in accordance with the value of the input data to-be-written and said column select signal, and each said data line is driven to the high level by the use of a corresponding said transistor, coupled thereto, and each said transistor functioning as said bit load in a case in which said data lines are to be driven to the high level.

Claim 19

A semiconductor memory according to claim 4, wherein in each column the corresponding said write driver further includes two NMOSFETs which are disposed so as to correspond respectively to said noninverting data line and said inverting data line, each one of said NMOSFETs is series-connected with a respective PMOSFET of said write driver to effect, in response to actuation by said column select signal, a pull-up and pull-down switching action, in accordance with the level of said write enable signal and the value of said write data when the corresponding column is selected by said column select signal.