Arithmetic processing module to be associated with a microprocessor central processing unit

Claim 2

An arithmetic processing module for use in a microprocessor for calculating in k cycles a product B of binary operands a, X, T, according to B=aX+T, based on an n-bit format, each of said binary operands a, X, T having a format of greater than n-bits, each bit of each of said binary operands having a significance level relative to every other of said bits, said operand a separated into k portions, each of said k portions having said n-bit format, said module comprising: data transfer means for communicating said product and operands within said module according to said n-bit format; storage means having k sections for storing said operand a, each section of said storage means having said n-bit format; selection means coupled to said storage means for cyclically selecting one of said k portions of operand a during each of said k cycles, said selection means cyclically selecting said portion of operand a according to increasing significance levels; multiplier means for receiving in each cycle said portion of operand a selected by said selection means and a portion of operand X having said n-bit format and having the same significance level as said portion of operand a and outputting a product of said portion of said operand X and said portion of operand a; adder means for adding a portion of operand T and said output of said multiplier means and outputting as a first output and a second output portions of said product B, said first output having a higher significance level than said second output; recycling means for retaining said first output for k cycles and for retaining said second output for k-1 cycles and then retrocoupling said first output and said second output to said adder means in place of said portion of said operand T.

Claim 3

The processing module of claim 1, wherein k is equal to 3.

Claim 4

The processing module of claim 1, wherein k is equal to 4.

Claim 5

The processing module of claim 1, wherein said recycling means includes a first buffer register for storing said first output of said adder means, a stack of k-1 further buffer registers for storing said second output of said adder means, a first multiplexer for outputting to said adder means one of said first buffer register and said portion of operand T and a second multiplexer for outputting to said stack of k-1 further buffer registers one of said first buffer register and said second output of said adder means.

Claim 6

The processing module of claim 4, wherein said operand a further includes an overflow bit connected to an additional input to said multiplier means, said first buffer register and said stack of stack of k-1 further buffer have a n+1 bit format, said adder means includes a first adder and a second adder, said first adder receives as inputs said output of said multiplier means having an 2n+1 format and an output of said k-1 stack of further buffer register having said n+1 bit format and has an output having said 2n+1 format, said second adder receives as inputs, said output of said first adder and said first buffer register, said second multiplexer receives as inputs, a portion of said first buffer register having an n-bit format, said second output of said adder means and an additional output equal to zero, said first multiplexer receives as inputs, said portion of operand T having said n bit format and said first buffer register having said n-bit format wherein said n+1th bit is ignored.

Claim 7

The processing module of claim 4 further including an overflow processing unit, said overflow processing unit including an overflow multiplexer having as inputs, said portion of operand X having said n-bit format and a value which equals zero having said n-bit format, an overflow adding means for adding said output of said adding means, an output of said overflow multiplexer, said overflow multiplexer having a first overflow output coupled to said first buffer register and a second overflow output having a 1 bit format, a carry register for storing said second overflow output and delay means for retaining said second overflow output for k cycles, said second overflow output input to said overflow adding means in a cycle immediately following said kth cycle.

Claim 8

The processing module of claim 4, wherein said first multiplexer outputs said portion of operand T during a first cycle and outputs said output of said first buffer register for each f said k-1 cycles and wherein said second multiplexer outputs said output of said first buffer register during said first cycle and outputs said second output of said adder means during each of said k-1 cycles.

Claim 9

The processing module of claim 1, wherein n equals 8.

Claim 10

The processing module of claim 1, further including an "exclusive OR" circuit having a first input connected to said second output of said adder means and a second input connected to one of said portion of operand X having said n-bit format and a predetermined constant.

Claim 11

An arithmetic processing module for use in a microprocessor for calculating in p cycles a product B of binary operands, a, X, T, according to B=aX+T, based on an n-bit format, each of said binary operands a, X, T having a format of greater than n-bits, each bit of each of said binary operands having a significance level relative to every other of said bits, said operand a separated into p portions, each of said p portions having said n-bit format, said module comprising: data transfer means for communicating said product and operands within said module according to said n-bit format; storage means having k sections for storing said p portions of said operand a, each section of said storage means having said n-bit format; selection means coupled to said storage means for cyclically selecting one of said k portions of operand a during each of said p cycles, said selection means cyclically selecting said portion of operand a according to increasing significance levels; multiplier means for receiving in each cycle said portion of operand a selected by said selection means and a portion of operand X having said n-bit format and having the same significance level as said portion of operand a and outputting a product of said portion of said operand X and said portion of operand a; adder means for adding a portion of operand T and said output of said multiplier means and outputting as a first output and a second output portions of said product B, said first output having a higher significance level than said second output; recycling means for retaining said first output for p cycles and for retaining said second output for p-1 cycles and then retrocoupling said first output and said second output to said adder means in place of said portion of said operand T.

Claim 12

An arithmetic processing module for use in a microprocessor for calculating in p cycles a product B of binary operands, a, X, T, according to B=aX+T, based on an n-bit format, each of said binary operands a, X, T having a format of greater than n-bits, each bit of each of said binary operands having a significance level relative to every other of said bits, said operand a separated into p portions, each of said p portions having said n-bit format, said module comprising: data transfer means for communicating said product and operands within said module according to said n-bit format; storage means having k sections for storing said p portions of said operand a, each section of said storage means having said n-bit format; selection means coupled to said storage means for cyclically selecting one of said k portions of operand a during each of said p cycles, said selection means cyclically selecting said portion of operand a according to increasing significance levels; multiplier means for receiving in each cycle said portion of operand a selected by said selection means and a portion of operand X having said n-bit format and having the same significance level as said portion of operand a and outputting a product of said portion of said operand X and said portion of operand a; adder means for adding a portion of operand T and said output of said multiplier means and outputting as a first output and a second output portions of said product B, said first output having a higher significance level than said second output; recycling means for retaining said first output for p cycles and for retaining said second output for p-1 cycles and then retrocoupling said first output and said second output to said adder means in place of said portion of said operand T.

Claim 13

The processing module of claim 10, wherein k is equal to 4 and wherein p is equal to 3.

Claim 14

The processing module of claim 11, wherein said recycling means includes a first buffer register for storing said first output of said adder means, a stack of k-1 further buffer registers for storing said second output of said adder means, a first multiplexer for outputting to said adder means one of said first buffer register and said portion of operand T and a second multiplexer for outputting to said stack of k-1 further buffer registers one of said first buffer register and said second output of said adder means.

Claim 15

The processing module of claim 12, wherein said recycling means includes a shortcircuit multiplexing means coupled between two of said k-1 further buffer registers for circumventing k-p of said k-1 further buffer registers.

Claim 16

The processing module of claim 10, wherein said recycling means includes a first buffer register for storing said first output of said adder means, a stack of k-1 further buffer registers for storing said second output of said adder means, a first multiplexer for outputting to said adder means one of said first buffer register and said portion of operand T and a second multiplexer for outputting to said stack of k-1 further buffer registers one of said first buffer register and said second output of said adder means.

Claim 17

The processing module of claim 14, wherein said recycling means includes a shortcircuit multiplexing means coupled between two of said k-1 further buffer registers for circumventing k-p of said k-1 further buffer registers.

Claim 18

The processing module of claim 14, wherein said operand a further includes an overflow bit connected to an additional input to said multiplier means, said first buffer register and said stack of stack of k-1 further buffer have a n+1 bit format, said adder means includes a first adder and a second adder, said first adder receives as inputs said output of said multiplier means having an 2n+1 format and an output of said k-1 stack of further buffer register having said n+1 bit format and has an output having said 2n+1 format, said second adder receives as inputs, said output of said first adder and said first buffer register, said second multiplexer receives as inputs, a portion of said first buffer register having an n-bit format, said second output of said adder means and an additional output equal to zero, said first multiplexer receives as inputs, said portion of operand T having said n bit format and said first buffer register having said n-bit format wherein said n+1th bit is ignored.

Claim 19

The processing module of claim 14 further including an overflow processing unit, said overflow processing unit including an overflow multiplexer having as inputs, said portion of operand X having said n-bit format and a value which equals zero having said n-bit format, an overflow adding means for adding said output of said adding means, an output of said overflow multiplexer, said overflow multiplexer having a first overflow output coupled to said first buffer register and a second overflow output having a 1 bit format, a carry register for storing said second overflow output and delay means for retaining said second overflow output for k cycles, said second overflow output input to said overflow adding means in a cycle immediately following said kth cycle.

Claim 20

The processing module of claim 14, wherein said first multiplexer outputs said portion of operand T during a first cycle and outputs said output of said first buffer register for each of said k-1 cycles and wherein said second multiplexer outputs said output of said first buffer register during said first cycle and outputs said second output of said adder means during each of said k-1 cycles.

Claim 21

The processing module of claim 10, wherein n equals 8.

Claim 22

The processing module of claim 10, further including an "exclusive OR" circuit having a first input connected to said second output of said adder means and a second input connected to one of said portion of operand X having said n-bit format and a predetermined constant.