US5113363A
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Method and apparatus for computing arithmetic expressions using on-line operands and bit-serial processing
Assignee: AIL Systems Inc
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Filing: 1991-03-05
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Granted: 1992-05-12
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Expires: 2011-03-05
Abstract
Abstract Method and apparatus for processing on-line operands A, B and C to produce the arithmetic expression S=(A×B)+C. In general, the apparatus includes an input processing unit, an on-line multiplication unit, and an on-line serial addition unit. The input processing unit is sequentially introducing the digits of operands, A, B and C into the apparatus, where each digit is represented in a redundant binary number format. The multiplication unit multiplies the sequence of digits of the operands A and B to produce the n-th product digit p n of the product P=A×B, with the most significant digit p o being computed first. The on-line addition unit adds the n-th product digit to the n-th digit of on-line operand C, so as to produce the n-th digit s n of the arithmetic expression S=(A×B)+C, with the most significant digit s o being produced first. In one embodiment, the input processing unit includes a selective conversion subunit for selectively converting the digits of operands A, B and C sequentially entering the computational device, so that each digit is represented in a redundant number format. In such an embodiment, the redundant binary number format is characterized by signed digit numbers, and the selective conversion subunit includes a binary-to-signed digit converter.
Inventors
- 👤 Francesco Orsino
- 👤 Chung-Tao D. Wang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 19:27
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/544; G06F7/5443; G06F7/4824; G06F2207/00; G06F2207/38; G06F2207/3804; G06F2207/3808; G06F2207/3852
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
406 words
Method of processing input logic signals representing the operands A, B and C, in signal processing logic circuit, produce an output logic signal representing the value of the arithmetic expressions S=(A×B)+C, the input signals representing operands A, B and C having a sequence of logic states corresponding to logic data bits represented by (a 0 , a 1 , . . . a n . . . , a N-1 ), (b 0 , b 1 , . . . b n . . . , b N-1 ) and (c 0 , c 1 , . . . c n . . . , c N-1 ) respectively, with the most significant logic data bit a 0 , b 0 , and c 0 , of each operand-representing input signal entering the signal processing logic circuit first, and where N is an integer, said method of logic signal processing comprising the sequence of steps: (a) sequentially introducing into said signal processing logic circuit said input logic signals representing operands A, B and C with the logic data bits arranged in a redundant binary number format; (b) multiplying said logic data bits of said input logic signals representing operands A and B using an on-line multiplication process in a multiplication logic circuit to produce an n-th product logic data bit p n of a product signal representing the product P=A×B, the product signal including a sequence of logic states corresponding to logic data bits represented by (p 0 , p 1 , . . . p n ) with a most significant digit p 0 being computed first by the multiplication logic circuit and where p n is the n-th logic data bit of the product signal; (c) adding said n-th product logic data bit of the product signal to an n-th logic data bit of the input logic signal representing operand C in an addition circuit using an on-line addition process so as to produce an n-th logic data bit s n of an output logic signal representing the arithmetic expressions S=(A×B)+C, the output logic signal including a sequence of logic states corresponding to logic data bits represented by (s 0 , S 1 , . . . s n ), a most significant logic data bit s 0 of the output logic signal being produced first; and (d) repeating steps (a), (b) and (c) N times so as to produce the output logic signal.
Claim 2
Dependent Claim
406 words
Method of processing input logic signals representing the operands A, B and C, in signal processing logic circuit, produce an output logic signal representing the value of the arithmetic expressions S=(A×B)+C, the input signals representing operands A, B and C having a sequence of logic states corresponding to logic data bits represented by (a 0 , a 1 , . . . a n . . . , a N-1 ), (b 0 , b 1 , . . . b n . . . , b N-1 ) and (c 0 , c 1 , . . . c n . . . , c N-1 ) respectively, with the most significant logic data bit a 0 , b 0 , and c 0 , of each operand-representing input signal entering the signal processing logic circuit first, and where N is an integer, said method of logic signal processing comprising the sequence of steps: (a) sequentially introducing into said signal processing logic circuit said input logic signals representing operands A, B and C with the logic data bits arranged in a redundant binary number format; (b) multiplying said logic data bits of said input logic signals representing operands A and B using an on-line multiplication process in a multiplication logic circuit to produce an n-th product logic data bit p n of a product signal representing the product P=A×B, the product signal including a sequence of logic states corresponding to logic data bits represented by (p 0 , p 1 , . . . p n ) with a most significant digit p 0 being computed first by the multiplication logic circuit and where p n is the n-th logic data bit of the product signal; (c) adding said n-th product logic data bit of the product signal to an n-th logic data bit of the input logic signal representing operand C in an addition circuit using an on-line addition process so as to produce an n-th logic data bit s n of an output logic signal representing the arithmetic expressions S=(A×B)+C, the output logic signal including a sequence of logic states corresponding to logic data bits represented by (s 0 , S 1 , . . . s n ), a most significant logic data bit s 0 of the output logic signal being produced first; and (d) repeating steps (a), (b) and (c) N times so as to produce the output logic signal.
Claim 3
Dependent Claim
41 words
The method of claim 1, wherein step (a) further comprises selectively converting the input logic signals representing operands A, B and C in a converter circuit so that each said logic data bit is represented in the redundant binary number format.
Claim 4
Dependent Claim
376 words
A signal processing logic circuit for processing input logic signals representing operands A, B and C to produce an output logic signal representing the arithmetic expressions S=(A×B)+C, the input signals representing operands A, B and C having a sequence of logic states corresponding to logic data bits represented by (a 0 , a 1 , . . . a n . . . , a N-1 ), (b 0 , b 1 , . . . b n . . . , b N-1 ) and (c 0 , c 1 , . . . c n . . . , c N-1 ), respectively, with the most significant logic data bit a 0 , b 0 , and c 0 of each operand-representing input signal entering the signal processing logic circuit first, and where N is an integer, said signal processing logic circuit comprising: an input processing circuit responsive to the input logic signals for sequentially introducing said logic data bits of the input signals representing operands A, B and C into said signal processing logic circuit, wherein said logic data bits are arranged in a redundant binary number format; an on-line multiplication circuit coupled to the input processing circuit for multiplying said logic data bits of said input logic signals representing operands A and B to produce an n-th logic data bit p n of a product signal representing the product P=A×B, the product signal including a sequence of logic states corresponding to logic data bits represented by (p 0 , p 1 , . . . p n ) with a most significant digit p 0 being computed first by the multiplication circuit; and an on-line addition circuit coupled to the multiplication circuit for adding the n-th product logic data bit p n to an n-th logic data bit of the input logic signal representing operand C, so as to produce an n-th logic data bit s n of an output logic signal representing the arithmetic expression S=(A×B)+C, the output logic signal including a sequence of logic states corresponding to logic data bits represented by (s 0 , s 1 , . . . s n ), a most significant logic data bit s 0 of the output logic signal being produced first.
Claim 5
Dependent Claim
376 words
A signal processing logic circuit for processing input logic signals representing operands A, B and C to produce an output logic signal representing the arithmetic expressions S=(A×B)+C, the input signals representing operands A, B and C having a sequence of logic states corresponding to logic data bits represented by (a 0 , a 1 , . . . a n . . . , a N-1 ), (b 0 , b 1 , . . . b n . . . , b N-1 ) and (c 0 , c 1 , . . . c n . . . , c N-1 ), respectively, with the most significant logic data bit a 0 , b 0 , and c 0 of each operand-representing input signal entering the signal processing logic circuit first, and where N is an integer, said signal processing logic circuit comprising: an input processing circuit responsive to the input logic signals for sequentially introducing said logic data bits of the input signals representing operands A, B and C into said signal processing logic circuit, wherein said logic data bits are arranged in a redundant binary number format; an on-line multiplication circuit coupled to the input processing circuit for multiplying said logic data bits of said input logic signals representing operands A and B to produce an n-th logic data bit p n of a product signal representing the product P=A×B, the product signal including a sequence of logic states corresponding to logic data bits represented by (p 0 , p 1 , . . . p n ) with a most significant digit p 0 being computed first by the multiplication circuit; and an on-line addition circuit coupled to the multiplication circuit for adding the n-th product logic data bit p n to an n-th logic data bit of the input logic signal representing operand C, so as to produce an n-th logic data bit s n of an output logic signal representing the arithmetic expression S=(A×B)+C, the output logic signal including a sequence of logic states corresponding to logic data bits represented by (s 0 , s 1 , . . . s n ), a most significant logic data bit s 0 of the output logic signal being produced first.
Claim 6
Dependent Claim
48 words
A signal processing logic circuit as defined by claim 3, wherein said input processing circuit comprises a selective conversion circuit for selectively converting the input logic signals representing operands A, B and C so that each said logic data bit is represented in the redundant binary number format.
Claim 7
Dependent Claim
45 words
A signal processing logic circuit as defined by claim 4, which further comprises: a word length control circuit for maintaining the word length of each input logic signal to N logic data bits, the word length control circuit being coupled to the selective conversion circuit.
Claim 8
Dependent Claim
78 words
A signal processing logic circuit as defined by claim 5, wherein said word length control circuit comprises: a detecting circuit for detecting the presence of a first pattern of the logic data bits of the input logic signals representing operands A, B and C, and for transforming the detected first pattern of logic data bits into a second pattern of logic data bits, the logic data bits of the second pattern being in the redundant binary number format.
Claim 9
Dependent Claim
58 words
A signal processing logic circuit as defined by claim 3, which further comprises a performance testing circuit for testing the performance of the signal processing logic circuit, the performance testing circuits being coupled to the input processing circuit and receiving the output logic signal, and being responsive to a predetermined test signal provided to said input processing circuit.
Claim 10
Dependent Claim
113 words
A signal processing logic circuit as defined by claim 7, wherein said performance testing circuit comprises: a test-data generating circuit for generating a test signal to be provided to said input processing circuit so as to obtain a predetermined output logic signal from said on-line addition circuit based on said test signal, said test-data generating circuit further providing an expected result signal based on said test signal; and a test-data/result comparison circuit for comparing said predetermined output logic signal obtained from said on-line addition circuit, with said expected result signal obtained from said test-data generating circuit, and generating an alarm signal when said predetermined output logic signal differs from said expected result signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-05-12 | 1995-11-11 | 1996-05-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-05-12 | 1999-11-11 | 2000-05-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-05-12 | 2003-11-11 | 2004-05-12 | $7700.00 | Window Closed / Lapsed |