Patent US2861824A successfully refreshed from Google Patents.
Patent US5285206A successfully refreshed from Google Patents.
US5285206A
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Phase detector for elastic store
Assignee: Nokia of America Corp
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Filing: 1992-08-25
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Granted: 1994-02-08
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Expires: 2012-08-25
Abstract
Abstract A bit resolution phase detector can be realized for a parallel elastic store by comparing a write bit clock and a read bit clock to determine when stuff bits are required; upon detection of phase alignment between the write and read clocks, the phase detector will output a signal which will enable the insertion of a data bit into the stuff opportunity bit and cause the write clock to lag the read clock by one bit period.
Inventors
- 👤 Richard W. Peters
- 👤 William B. Weeber
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 12:41
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/07; H04J3/076
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
250 words
A mapping circuit for mapping a lower-speed serial signal (28) to a higher-speed parallel signal (40) organized in frames having plural rows of bits mapped from the lower-speed signal, the mapping circuit comprising: a shift register (26), responsive to the lower-speed serial signal (28) for providing the lower-speed signal as a converted parallel signal (12); a parallel elastic store (10), responsive to the converted parallel signal (12), for providing a high-speed signal in parallel (18); a bit stuffer (20), responsive to the high-speed signal (18) in parallel from the elastic store and responsive to a control signal (38), for controlling use of a stuff bit opportunity appearing at least once per row; a first divider (50), responsive to a bit clock (32) related to the lower-speed signal (28), for providing a first divided signal (54); a second divider (52), responsive to a bit clock (30) related to the higher-speed signal (40), for providing a second divided signal (56); a phase detector (48), responsive to the first and second divided signals (54, 56), for comparing their phases and for providing a stuff bit enable signal (60) in the presence of zero-phase difference therebetween; and a stuff control (46), responsive to the stuff bit enable signal (60), a near-full signal (62) and a near-empty signal (64), for providing the control signal (38) and wherein the bit stuffer (20) is responsive tot he control signal (38) for providing a stuff bit or a data bit in the higher-speed parallel signal (40) output therefrom.
Claim 2
Dependent Claim
250 words
A mapping circuit for mapping a lower-speed serial signal (28) to a higher-speed parallel signal (40) organized in frames having plural rows of bits mapped from the lower-speed signal, the mapping circuit comprising: a shift register (26), responsive to the lower-speed serial signal (28) for providing the lower-speed signal as a converted parallel signal (12); a parallel elastic store (10), responsive to the converted parallel signal (12), for providing a high-speed signal in parallel (18); a bit stuffer (20), responsive to the high-speed signal (18) in parallel from the elastic store and responsive to a control signal (38), for controlling use of a stuff bit opportunity appearing at least once per row; a first divider (50), responsive to a bit clock (32) related to the lower-speed signal (28), for providing a first divided signal (54); a second divider (52), responsive to a bit clock (30) related to the higher-speed signal (40), for providing a second divided signal (56); a phase detector (48), responsive to the first and second divided signals (54, 56), for comparing their phases and for providing a stuff bit enable signal (60) in the presence of zero-phase difference therebetween; and a stuff control (46), responsive to the stuff bit enable signal (60), a near-full signal (62) and a near-empty signal (64), for providing the control signal (38) and wherein the bit stuffer (20) is responsive tot he control signal (38) for providing a stuff bit or a data bit in the higher-speed parallel signal (40) output therefrom.
Claim 3
Dependent Claim
35 words
The circuit of claim 1, further comprising a second phase detector (42), responsive to a write address signal (14) and to a read address signal (22) for providing the near-full and near-empty signals (62, 64).
Claim 4
Dependent Claim
27 words
The circuit of claim 1, wherein the first divider (50) is responsive to the stuff bit enable signal for disabling itself for one bit clock (30) period.
Claim 5
Independent Claim
108 words
A method for mapping a lower-speed serial signal (28) to a higher-speed parallel signal (40) organized in frames having plural rows of bits mapped from the lower-speed signal, comprising the steps of: detecting a nominally periodic phase alignment between a write clock (30) quotient signal (54) and a read clock (32) quotient signal (56); providing an enable signal (60) in the presence of phase alignment to enable the insertion of a data bit into a stuff opportunity bit location in the higher-speed parallel signal (40); and causing the divided write clock (54) to lag the divided read clock (56) by one bit period of the write clock (30).
Claim 6
Independent Claim
108 words
A method for mapping a lower-speed serial signal (28) to a higher-speed parallel signal (40) organized in frames having plural rows of bits mapped from the lower-speed signal, comprising the steps of: detecting a nominally periodic phase alignment between a write clock (30) quotient signal (54) and a read clock (32) quotient signal (56); providing an enable signal (60) in the presence of phase alignment to enable the insertion of a data bit into a stuff opportunity bit location in the higher-speed parallel signal (40); and causing the divided write clock (54) to lag the divided read clock (56) by one bit period of the write clock (30).
Claim 7
Dependent Claim
172 words
Apparatus for mapping a lower-speed serial signal to a higher-speed parallel signal organized in frames having plural rows of bits mapped from the lower speed signal, comprising: a phase detector (96), responsive to a write clock quotient signal (76) and a read clock quotient signal (88), for providing an enable signal (94) in the presence of phase alignment between the quotient signals (76, 88); a write clock divide circuit (92), responsive to a write clock (71) and to the enable signal (94), for providing the write clock quotient signal (76) and for causing the write clock quotient signal (76) to lag the read clock quotient signal (88) by one bit period of the write clock (71) in the presence of the enable signal (94); and logic means (96), responsive to the enable signal (94) and to a near full signal (96) and a near empty signal (98), for providing a control signal (95a) for controlling the insertion of a data bit into a stuff opportunity bit location in the higher-speed parallel signal.
Claim 8
Dependent Claim
172 words
Apparatus for mapping a lower-speed serial signal to a higher-speed parallel signal organized in frames having plural rows of bits mapped from the lower speed signal, comprising: a phase detector (96), responsive to a write clock quotient signal (76) and a read clock quotient signal (88), for providing an enable signal (94) in the presence of phase alignment between the quotient signals (76, 88); a write clock divide circuit (92), responsive to a write clock (71) and to the enable signal (94), for providing the write clock quotient signal (76) and for causing the write clock quotient signal (76) to lag the read clock quotient signal (88) by one bit period of the write clock (71) in the presence of the enable signal (94); and logic means (96), responsive to the enable signal (94) and to a near full signal (96) and a near empty signal (98), for providing a control signal (95a) for controlling the insertion of a data bit into a stuff opportunity bit location in the higher-speed parallel signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-02-07 | 1997-08-09 | 1998-02-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-02-07 | 2001-08-09 | 2002-02-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-02-07 | 2005-08-09 | 2006-02-08 | $7700.00 | Window Closed / Lapsed |