← Back to Patent Explorer
US5285102A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of forming a planarized insulation layer

Assignee: Texas Instruments Inc
•
Filing: 1992-12-08
•
Granted: 1994-02-08
•
Expires: 2012-12-08
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A method for forming a planar insulating layer over the surface of a semiconductor workpiece 8 which includes at least one low region 13 is discussed herein. The first step is to form a layer of blocking material 14 on the surface of the workpiece 8. A first material region 20 is then formed in the low region 13 and an insulating layer 21 is formed over the surface of the workpiece 8 including the first material region 20. The workpiece 8 is then heated in the presence of an active ambient such that the insulation layer 21 reflows and also so that the first material 20 region reacts with the active ambient to create an internal stress in said insulation layer 21. Other systems and methods are also disclosed.

Inventors

  • 👤 Peter S. Ying

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-03 22:09
CPC Classifications
H; H10; H10P; H10P95/00; H10P95/06; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/014; H10W10/0143; H10W10/10; H10W10/17; H10W20/00; H10W20/40; H10W20/45; H10W20/47; H10W20/48; Y; Y10; Y10S; Y10S148/00; Y10S148/133

Claims Analysis

Total Claims: 17
Claim 1
Independent Claim 74 words
A semiconductor device comprising: a semiconductor layer; a trench region formed in a surface of said semiconductor layer; an insulating layer formed on said surface of said semiconductor layer; a substantially planar borophosphosilicate glass (BPSG) layer formed over said insulating layer, said BPSG layer having a first material region formed within said BPSG layer, said first material region creating an internal stress within said in said BPSG layer to substantially planarize said BPSG layer.
Claim 2
Dependent Claim 74 words
A semiconductor device comprising: a semiconductor layer; a trench region formed in a surface of said semiconductor layer; an insulating layer formed on said surface of said semiconductor layer; a substantially planar borophosphosilicate glass (BPSG) layer formed over said insulating layer, said BPSG layer having a first material region formed within said BPSG layer, said first material region creating an internal stress within said in said BPSG layer to substantially planarize said BPSG layer.
Claim 3
Dependent Claim 13 words
The device of claim 1 wherein said semiconductor layer comprises a silicon layer.
Claim 4
Dependent Claim 13 words
The device of claim 2 wherein said insulating layer comprises a nitride layer.
Claim 5
Dependent Claim 15 words
The device of claim 1 wherein said first material region comprises a silicon dioxide region.
Claim 6
Dependent Claim 15 words
The device of claim 1 wherein said first material region is disposed in said trench.
Claim 7
Dependent Claim 84 words
A semiconductor device comprising: a semiconductor layer; at least two stacked layers formed on a surface of said semiconductor layer, said stacked layers separated by a low region; an insulating layer formed on said surface of said semiconductor layer; a substantially planar borophosphosilicate glass (BPSG) layer formed over said insulating layer, said BPSG layer having a first material region formed within said BPSG layer, said first material region creating an internal stress within said in said BPSG layer to substantially planarize said BPSG layer.
Claim 8
Dependent Claim 84 words
A semiconductor device comprising: a semiconductor layer; at least two stacked layers formed on a surface of said semiconductor layer, said stacked layers separated by a low region; an insulating layer formed on said surface of said semiconductor layer; a substantially planar borophosphosilicate glass (BPSG) layer formed over said insulating layer, said BPSG layer having a first material region formed within said BPSG layer, said first material region creating an internal stress within said in said BPSG layer to substantially planarize said BPSG layer.
Claim 9
Dependent Claim 13 words
The device of claim 6 wherein said semiconductor layer comprises a silicon layer.
Claim 10
Dependent Claim 13 words
The device of claim 7 wherein said insulating layer comprises a nitride layer.
Claim 11
Dependent Claim 15 words
The device of claim 6 wherein said first material region comprises a silicon dioxide region.
Claim 12
Dependent Claim 79 words
A semiconductor device comprising: a semiconductor workpiece including at least two elevated regions separated by at least one low region disposed on a surface thereof; an insulating layer formed on the surface of said workpiece; a substantially planar borophosphosilicate glass (BPSG) layer formed over said insulating layer, said BPSG layer having a first material region formed within said BPSG layer, said first material creating an internal stress within said in said BPSG layer to substantially planarize said BPSG layer.
Claim 13
Dependent Claim 79 words
A semiconductor device comprising: a semiconductor workpiece including at least two elevated regions separated by at least one low region disposed on a surface thereof; an insulating layer formed on the surface of said workpiece; a substantially planar borophosphosilicate glass (BPSG) layer formed over said insulating layer, said BPSG layer having a first material region formed within said BPSG layer, said first material creating an internal stress within said in said BPSG layer to substantially planarize said BPSG layer.
Claim 14
Dependent Claim 12 words
The device of claim 10 wherein said elevated regions comprise stack structures.
Claim 15
Dependent Claim 12 words
The device of claim 10 wherein said low region comprises a trench.
Claim 16
Dependent Claim 12 words
The device of claim 10 wherein said first material comprises silicon dioxide.
Claim 17
Dependent Claim 13 words
The device of claim 10 wherein said insulating layer comprises a nitride layer.

References Cited (Backward Citations)

US4239559A Cited
US5006913A Cited
US4982250A Cited
US5068711A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1997-02-07 1997-08-09 1998-02-08 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2001-02-07 2001-08-09 2002-02-08 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2005-02-07 2005-08-09 2006-02-08 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag