US5283879A — Protected method for fast writing of data for mas…

Claim 1

Independent Claim 429 words

A method of fast writing of information for at least one mass memory apparatus (DMM 1 ) including a plurality of mass memory units and belonging to an information processing system including at least one central host (H 1 , H 2 ), a first and second control unit (UC 1 , UC 2 ), connected to a first and second parallel bus (B 1 , B 2 ), wherein said control units (UC1, UC2) include a first and second central processor (PR 1 and PR 2 ), respectively, the central host (H 1 , H 2 ) being connected to each of the buses via at least one first host adaptor (HA 1 , HA 2 ) of the first control unit (UC 1 , UC 2 ), and at least a first and second mass memory device for controlling and organizing writing of information on each mass memory unit, said mass memory device being connected to at least one of said first and second parallel buses, wherein said at least one host adaptor, the mass memory device and the mass memory units are on the same data path; comprising the steps of I) storing a block of data to be written, sent from the central host, in the first host adaptor (HA 1 , HA 2 ) and then in the first mass memory device (DA 1 , DA 2 ) by communication between the central host (H 1 , H 2 ) and the host adaptors (HA 1 , HA 2 ), and between the host adaptors and the mass memory device (DA 1 , DA 2 ), respectively; II) causing the first mass memory device (DA 1 , DA 2 ) to send a request to the first central processor for reservation of the mass memory (D 1 -D 5 ) for writing information therein; III) informing the host adaptor (HA 1 ), by signal from the mass memory device, that the reservation request has been made, and sending an acknowledgement signal from the host adaptor HA 1 to the central host (H 1 ); and IV) writing the block of data in its entirety in the mass memory under the control of the first mass memory device (DA 1 ), in all cases when the first mass memory adapter is functioning properly, and by the second mass memory device (DA 2 ) when the first mass memory device (DA 1 ) is defective, wherein if said first mass memory device is defective the block of data is transferred to said second mass memory device.

Claim 2

Independent Claim 429 words

A method of fast writing of information for at least one mass memory apparatus (DMM 1 ) including a plurality of mass memory units and belonging to an information processing system including at least one central host (H 1 , H 2 ), a first and second control unit (UC 1 , UC 2 ), connected to a first and second parallel bus (B 1 , B 2 ), wherein said control units (UC1, UC2) include a first and second central processor (PR 1 and PR 2 ), respectively, the central host (H 1 , H 2 ) being connected to each of the buses via at least one first host adaptor (HA 1 , HA 2 ) of the first control unit (UC 1 , UC 2 ), and at least a first and second mass memory device for controlling and organizing writing of information on each mass memory unit, said mass memory device being connected to at least one of said first and second parallel buses, wherein said at least one host adaptor, the mass memory device and the mass memory units are on the same data path; comprising the steps of I) storing a block of data to be written, sent from the central host, in the first host adaptor (HA 1 , HA 2 ) and then in the first mass memory device (DA 1 , DA 2 ) by communication between the central host (H 1 , H 2 ) and the host adaptors (HA 1 , HA 2 ), and between the host adaptors and the mass memory device (DA 1 , DA 2 ), respectively; II) causing the first mass memory device (DA 1 , DA 2 ) to send a request to the first central processor for reservation of the mass memory (D 1 -D 5 ) for writing information therein; III) informing the host adaptor (HA 1 ), by signal from the mass memory device, that the reservation request has been made, and sending an acknowledgement signal from the host adaptor HA 1 to the central host (H 1 ); and IV) writing the block of data in its entirety in the mass memory under the control of the first mass memory device (DA 1 ), in all cases when the first mass memory adapter is functioning properly, and by the second mass memory device (DA 2 ) when the first mass memory device (DA 1 ) is defective, wherein if said first mass memory device is defective the block of data is transferred to said second mass memory device.

Claim 3

Dependent Claim 108 words

The method of claim 1, wherein the first step I includes the following successive steps: 1) sending a writing request from the host H 1 to the first host adaptor (HA 1 ); 2) sending a transfer request from the host adaptor (HA 1 ) to the host to transfer the block of data to be written; 3) storing the block of data in its entirety, first in a first host buffer (MTH 1 ) within the first host adaptor (HA 1 , HA 2 ), and then also in a first memory buffer (MTD 1 ) within the first memory device (DA 1 , DA 2 ).

Claim 4

Dependent Claim 82 words

The method of claim 1, wherein when the first mass memory adaptor (DA 1 ) is defective after step III, said method includes the steps of: a) sending the block of data by the host adaptor (HA 1 ) to the second mass memory device (DA 2 ); and b) causing the second mass memory device (DA 2 ) to control the performance of steps II, III, IV, instead of having the steps controlled by the first memory device (DA 1 ).

Claim 5

Dependent Claim 221 words

The method of claim 1, wherein the first control unit (UC 1 ) includes at least one first backup rotary disk memory (MDS 1 ) connected both to the first central processor (PR 1 ) of said first control unit and to an interface board (DEI 2 ) of the second control unit (UC 2 ) for interfacing with the first and second buses (B 1 , B 2 ), and said second control unit further includes at least one second backup rotary disk memory (MSD 2 ) connected both to the second central processor (PR 2 ) of the second control unit and to an interface board (DEI 1 ) of the first control unit for interfacing with the first and second buses connected to the first control unit, independent power supplies for said first and second control units, each control unit having its own protection battery, such that if the power supplies are out or defective during step IV, the following steps are performed: V) causing the first central processor (PR 1 ) to extract the data block to be written, contained in the first memory buffer (MTD 1 ), and transferring the extracted data integrally to the backup disk memory (MSD 1 ); VI) then causing the first central processor to disconnect the protection battery (BAT 1 ).

Claim 6

Dependent Claim 37 words

The method of claim 1, characterized in that if one or the other of the two buses is defective, during step IV, continuing step IV, under the direction of the first mass memory device (DA 1 ).

Claim 7

Dependent Claim 77 words

The method of claim 1, characterized in that when the first host adaptor is connected to both of the two buses (B 1 , B 2 ), and the first and second memory devices (DA 1 ; DA 2 ) are connected, one to the first bus (B 1 ), and the other to the second bus (B 2 ), respectively, the second mass memory device performs steps I-IV, V-IX, instead of the first mass memory device.

Claim 8

Dependent Claim 37 words

The method of claim 2, characterized in that if one or the other of the two buses is defective, during step IV, continuing step IV, under the direction of the first mass memory device (DA 1 ).

Claim 9

Dependent Claim 77 words

The method of claim 2, characterized in that when the first host adaptor is connected to both of the two buses (B 1 , B 2 ), and the first and second memory devices (DA 1 ; DA 2 ) are connected, one to the first bus (B 1 ), and the other to the second bus (B 2 ), respectively, the second mass memory device performs step I-IV, V-IX, instead of the first mass memory device.

Claim 10

Dependent Claim 82 words

The method of claim 2, wherein when the first mass memory device (DA 1 ) is defective after steps III, said method includes the steps of: a) sending the block of data by the host adaptor (HA 1 ) to the second mass memory device (DA 2 ); and b) causing the second mass memory device (DA 2 ) to control the performance of steps II, III, IV, instead of having the steps controlled by the first memory device (DA 1 ).

Claim 11

Dependent Claim 221 words

The method of claim 2, wherein the first control unit (UC 1 ) includes at least one first backup rotary disk memory (MDS 1 ) connected both to the first central processor (PR 1 ) of said first control unit and to an interface board (DEI 2 ) of the second control unit (UC 2 ) for interfacing with the first and second buses (B 1 , B 2 ), and said second control unit further includes at least one second backup rotary disk memory (MSD 2 ) connected both to the second central processor (PR 2 ) of the second control unit and to an interface board (DEI 1 ) of the first control unit for interfacing with the first and second buses connected to the first control unit, independent power supplies for said first and second control units, each control unit having its own protection battery, such that if the power supplies are out or defective during step IV, the following steps are performed: V) causing the first central processor (PR 1 ) to extract the data block to be written, contained in the first memory buffer (MTD 1 ), and transferring the extracted data integrally to the backup disk memory (MSD 1 ); VI) then causing the first central processor to disconnect the protection battery (BAT 1 ).

Claim 12

Dependent Claim 77 words

The method of claim 10, characterized in that when the first host adaptor is connected to both of the two buses (B 1 , B 2 ), and the first and second memory devices (DA 1 ; DA 2 ), are connected, one to the first bus (B 1 ), and the other to the second bus (B 2 ), respectively, the second mass memory device performs step I-IV, V-IX, instead of the first mass memory device.

Claim 13

Dependent Claim 97 words

The method of claim 10, characterized in that as soon as the power supplies are restored to normal operation, the following steps are performed VII) initializing the first and second control units (UC 1 , UC 2 ); VIII) informing the central host (H 1 ) from the first processor of reinitiating of the first and second control units and transferring the data contained in the backup disk memory (MSD 1 ) to a first host buffer (MTH 1 ) and to a first memory buffer (MTD 1 ); and IX) repeating step II, III and IV.

Claim 14

Dependent Claim 30 words

The method of claim 10, wherein if the first processor (PR 1 ) is defective, repeating steps V and VI by the second processor (PR 2 ), and vice versa.

Claim 15

Dependent Claim 77 words

The method of claim 12, characterized in that when the first host adaptor is connected to both of the two buses (B 1 , B 2 ), and the first and second memory devices (DA 1 ; D 2 ) are connected, one to the first bus (B 1 ), and the other to the second bus (B 2 ), respectively, the second mass memory device performs step I-IV, V-IX, instead of the first mass memory device.

Claim 16

Dependent Claim 31 words

The method of claim 12, wherein if the first processor (PR 1 ) is defective, repeating the steps VII, VIII, IX by the second processor (PR 2 ), and vice versa.

Claim 17

Dependent Claim 218 words

The method of claim 3, wherein the first control unit (UC 1 ) includes at least one first backup rotary disk memory (MSD 1 ) connected both to the first central processor (PR 1 ) of said first control unit and to an interface board (DEI 2 ) of the second control unit (UC 2 ) for interfacing with the first and second buses (B 1 , B2), and said second control unit further includes at least one second backup rotary disk memory (MSD 2 ) connected both to the second central processor (PR 2 ) of the second control unit and to an interface board (DEI 1 ) of the first control unit for interfacing with the first and second buses connected to the first control unit, independent power supplies for said first and second control units, each control unit having its own protection battery, such that if the power supplies are out or defective during step IV, the following steps are performed: V) causing the first processor (PR 1 ) to extract the data block to be written, contained in the first memory buffer (MTD 1 ), and transferring the extracted data integrally to the backup disk memory (MSD 1 ); VI) then causing the first central processor to disconnect the protection battery (BAT 1 ).

Claim 18

Dependent Claim 30 words

The method of claim 16, wherein if the first processor (PR 1 ) is defective, repeating steps V and VI by the second processor (PR 2 ), and vice versa.

Claim 19

Dependent Claim 97 words

The method of claim 16, characterized in that as soon as the power supplies are restored to normal operation, the following steps are performed VI) initializing the first and second control units (UC 1 , UC 2 ); VIII) informing the central host (H 1 ) from the first processor of reinitiating of the first and second control units and transferring the data contained in the backup disk memory (MSD 1 ) to a first host buffer (MTH 1 ) and to a first memory buffer (MTD 1 ); and IX) repeating steps II, III and IV.

Claim 20

Dependent Claim 77 words

The method of claim 16, characterized in that when the first host adaptor is connected to both of the two buses (B 1 , B 2 ), and the first and second memory devices (DA 1 ; DA 2 ) are connected, one to the first bus (B 1 ), and the other to the second bus (B 2 ), respectively, the second mass memory device performs step I-IV, V-IX, instead of the first mass memory device.

Claim 21

Dependent Claim 30 words

The method of claim 18, wherein if the first processor (PR 1 ) is defective, repeating steps VII, VIII, IX by the second processor (PR 2 ), and vice versa.

Claim 22

Dependent Claim 77 words

The method of claim 18, characterized in that when the first host adaptor is connected to both of the two buses (B 1 , B 2 ), and the first and second memory devices (DA 1 ; D 2 ) are connected, one to the first bus (B 1 ), and the other to the second bus (B 2 ), respectively, the second mass memory device performs steps I-IV, V-IX, instead of the first mass memory device.

Claim 23

Dependent Claim 30 words

The method of claim 4, wherein if the first processor (PR 1 ) is defective, repeating steps V and VI by the second processor (PR 2 ), and vice versa.

Claim 24

Dependent Claim 97 words

The method of claim 4, characterized in that as soon as the power supplies are restored to normal operation, the following steps are performed VII) initializing the first and second control units (UC 1 , UC 2 ); VIII) informing the central host (H 1 ) from the first processor of reinitiating of the first and second control units and transferring the data contained in the backup disk memory (MSD 1 ) to a first host buffer (MTH 1 ) and to a first memory buffer (MTD 1 ); and IX) repeating steps II, III and IV.

Claim 25

Dependent Claim 77 words

The method of claim 4, characterized in that when the first host adaptor is connected to both of the two buses (B 1 , B 2 ), and the first and second memory devices (DA 1 ; DA 2 ) are connected, one to the first bus (B 1 ), and the other to the second bus (B 2 ), respectively, the second mass memory device performs steps I-IV, V-IX, instead of the first mass memory device.

Claim 26

Dependent Claim 30 words

The method of claim 23, wherein if the first processor (PR 1 ) is defective, repeating steps V and VI by the second processor (PR 2 ), and vice versa.

Claim 27

Dependent Claim 77 words

The method of claim 23, characterized in that when the first host adaptor is connected to both of the two buses (B 1 , B 2 ), and the first and second memory devices (DA 1 ; DA 2 ) are connected, one to the first bus (B 1 ), and the other to the second bus (B 2 ), respectively, the second mass memory device performs steps I-IV, V-IX, instead of the first mass memory device.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1997-01-31	1997-08-02	1998-02-01	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2001-01-31	2001-08-02	2002-02-01	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2005-01-31	2005-08-02	2006-02-01	$7700.00	Window Closed / Lapsed

Protected method for fast writing of data for mass memory apparatus

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