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US5283785A
Expired / Lapsed
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Bus bypassing matrix switch in add-drop multiplexer
Assignee: GPT Ltd
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Filing: 1991-03-14
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Granted: 1994-02-01
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Expires: 2011-03-14
Abstract
Abstract An add/drop multiplex includes a matrix switch, the drop side of which is connected via buses to respective time slot assignment function circuits which are interconnected by at least one bus capable of transferring traffic between the add and the drop functions of the multiplex.
Inventors
- 👤 Stephen P. Ferguson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 17:39
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/02; H04J3/08
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
140 words
An add-drop multiplexer, comprising: a matrix switch for routing traffic through the multiplexer, said switch having a drop side; input tributaries operatively connected to the switch and having an input tributary ports for adding data to the traffic; output tributaries operatively connected to the switch and having output tributary ports for dropping data to the traffic; a pair of time slot assignment circuits operatively connected to the drop side of the switch, one of the assignment circuits being operative for assigning time slots for data added via the input tributary ports, and the other of the assignment circuits being operative for assigning time slots for data dropped via the output tributary ports; and a bus connected between the assignment circuits and bypassing the switch, said bus being operative for conveying the data between the tributaries without passing through the switch.
Claim 2
Dependent Claim
140 words
An add-drop multiplexer, comprising: a matrix switch for routing traffic through the multiplexer, said switch having a drop side; input tributaries operatively connected to the switch and having an input tributary ports for adding data to the traffic; output tributaries operatively connected to the switch and having output tributary ports for dropping data to the traffic; a pair of time slot assignment circuits operatively connected to the drop side of the switch, one of the assignment circuits being operative for assigning time slots for data added via the input tributary ports, and the other of the assignment circuits being operative for assigning time slots for data dropped via the output tributary ports; and a bus connected between the assignment circuits and bypassing the switch, said bus being operative for conveying the data between the tributaries without passing through the switch.
Claim 3
Dependent Claim
26 words
The multiplexer according to claim 1, wherein the switch is connected in a ring having slave multiplexers, and wherein the switch is a ring master multiplexer.
Claim 4
Dependent Claim
37 words
The multiplexer according to claim 1, wherein the switch has a link side and four ports, two of the ports being located on the link side, and the remaining two ports being located on the drop side.
Claim 5
Dependent Claim
31 words
The multiplexer according to claim 1, wherein the drop side has two drop ports, and wherein each assignment circuit is connected via a pair of assignment buses to the drop ports.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-01-31 | 1997-08-02 | 1998-02-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-01-31 | 2001-08-02 | 2002-02-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-01-31 | 2005-08-02 | 2006-02-01 | $7700.00 | Window Closed / Lapsed |