Patent US5283760A successfully refreshed from Google Patents.
US5283760A
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Data transmission circuit
Assignee: Samsung Electronics Co Ltd
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Filing: 1992-07-27
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Granted: 1994-02-01
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Expires: 2012-07-27
Abstract
Abstract A data transmission circuit capable of a high-speed data input/output operation and a large-scaled integration for use in a semiconductor memory device, is disclosed. The data transmission circuit has at least one memory cell 51, a word line 52, a pair of bit lines 65, 66, a sense amplifier 55, and a pair of isolation transistors 53, 54. Further, the circuit includes a pair of common input/output lines 67, 68 for transmitting input or output data with a complementary logic operation, a discharging transistor 56 receiving a control signal at its gate and having a channel connected with a ground voltage node, for transferring an electric potential applied to one end of the channel into the ground voltage level, and a pair of transmission transistors 59, 60 receiving the control signal at their respective gates and having each channel connected with the common input/output lines. Two pairs of input transistors 61, 62 and 63, 64 are connected with the bit lines, their channels each being connected between the bit lines 65, 66 and the transmission transistors 59, 60, their gates each connected with the input/output lines. A pair of output transistors 57, 58 each have a gate electrode connected to the bit lines, and having a channel connected between the channel of the discharging transistor 56 and the channel of the transmission transistors 59, 60. To control electrodes of the discharging transistor 56 and the first and second transmission transistor 59, 60 is applied a column selection line (CSL) signal.
Inventors
- 👤 Dae-Je Chin
- 👤 Byung-Hyuk Min
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 23:07
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4096
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
247 words
A data transmission circuit for use in a semiconductor memory device for writing and reading data into and out of a memory cell in accordance with a control signal, provided with a plurality of memory cells, a pair of bit line respectively connected to the memory cell, and a sense amplifier for amplifying an electric potential difference in between the bit lines, the circuit comprising: common input/output line means having a pair of input/output lines for transmitting input or output data with a complementary logic operation; a discharging transistor receiving the control signal at its gate and having a channel connected with a ground voltage node, for transferring an electric potential applied to one end of the channel into the ground voltage level; a transmission transistor means having a pair of transistors receiving the control signal at their respective gates and having each channel connected with the common input/output lines; input transistor means including two pairs of input transistors connected with the bit lines, each channel of the input transistors being connected between one of the bit lines and one of the input/output lines, each gate electrode of the input transistors receiving an electric potential on one of the input/output lines; and output transistor means including a pair of transistors each having a gate electrode connected to one of the bit lines, and having a channel connected between one end of the channel of the discharging transistor and one end of the channel of the transmission transistors.
Claim 2
Dependent Claim
247 words
A data transmission circuit for use in a semiconductor memory device for writing and reading data into and out of a memory cell in accordance with a control signal, provided with a plurality of memory cells, a pair of bit line respectively connected to the memory cell, and a sense amplifier for amplifying an electric potential difference in between the bit lines, the circuit comprising: common input/output line means having a pair of input/output lines for transmitting input or output data with a complementary logic operation; a discharging transistor receiving the control signal at its gate and having a channel connected with a ground voltage node, for transferring an electric potential applied to one end of the channel into the ground voltage level; a transmission transistor means having a pair of transistors receiving the control signal at their respective gates and having each channel connected with the common input/output lines; input transistor means including two pairs of input transistors connected with the bit lines, each channel of the input transistors being connected between one of the bit lines and one of the input/output lines, each gate electrode of the input transistors receiving an electric potential on one of the input/output lines; and output transistor means including a pair of transistors each having a gate electrode connected to one of the bit lines, and having a channel connected between one end of the channel of the discharging transistor and one end of the channel of the transmission transistors.
Claim 3
Dependent Claim
39 words
The data transmission circuit as set forth in claim 1, wherein said control signal corresponds to a column select line (CSL) signal that is adapted to be assigned just following selection of a word line in the memory cell.
Claim 4
Dependent Claim
40 words
The data transmission circuit as set forth in claim 1, wherein said transmission transistor means includes first and second transistors each having a channel connected to either one of the input/output lines and a gate electrode receiving said control signal.
Claim 5
Dependent Claim
63 words
The data transmission circuit as set forth in claim 3, wherein said input transistor means includes first and second transistor pairs, said each pair including two NMOS transistors each having a gate connected to either one of the common input/output lines, and having a channel connected between either one of the bit lines and a drain or source electrode of the transmission transistor.
Claim 6
Dependent Claim
33 words
The data transmission circuit as set forth in claim 4, wherein said NMOS transistors of said first and second transistor pairs are adapted to turn on only during a data input timing sequence.
Claim 7
Dependent Claim
81 words
The data transmission circuit as set forth in claim 3, wherein said output transistor means includes a first output transistor having a gate connected to one of the bit lines and a channel connected between the discharging transistor and the first transistor of said transmission transistor means, and a second output transistor having a gate connected to the other one of the bit lines and a channel connected between the discharging transistor and the second transistor of said transmission transistor means.
Claim 8
Dependent Claim
32 words
The data transmission circuit as set forth in claim 6, wherein said first and second output transistors are adapted to turn on in a complementary manner during data input and output operation.
Claim 9
Dependent Claim
49 words
The data transmission circuit as set forth in claim 6, wherein when either one of the first and second output transistors is turned off, a corresponding one of the common input/output lines coupled to a channel of the turned-off output transistor is electrically isolated from the ground voltage node.
Claim 10
Dependent Claim
237 words
A data transmission circuit for use in a semiconductor memory device having a plurality of memory cells, a pair of bit line connectable to the memory cell, a sense amplifier for amplifying a potential difference between the bit lines, and a pair of common input/output lines with a complementary logic level for data transmission, an input/output operation of the data being controlled by a column selection line (CSL) signal, said circuit comprising: a first switching transistor having a control gate coupled to one of the bit lines, and a channel connected between a ground voltage node and one of the common input/output lines; a second switching transistor having a control gate coupled to the other one of the bit lines, and a channel connected between the ground voltage node and the other one of the common input/output lines; a first pair of input transistors each having a control gate connected to the pair of common input/output lines, and a channel connected between one of the bit lines and either one channel of the first and second switching transistors, for carrying out a data input transmission therethrough; and a second pair of input transistors each having a control gate connected to the pair of common input/output lines, and a channel connected between the other one of the bit lines and either one channel of the first and second switching transistors, for carrying out a data input transmission therethrough.
Claim 11
Dependent Claim
237 words
A data transmission circuit for use in a semiconductor memory device having a plurality of memory cells, a pair of bit line connectable to the memory cell, a sense amplifier for amplifying a potential difference between the bit lines, and a pair of common input/output lines with a complementary logic level for data transmission, an input/output operation of the data being controlled by a column selection line (CSL) signal, said circuit comprising: a first switching transistor having a control gate coupled to one of the bit lines, and a channel connected between a ground voltage node and one of the common input/output lines; a second switching transistor having a control gate coupled to the other one of the bit lines, and a channel connected between the ground voltage node and the other one of the common input/output lines; a first pair of input transistors each having a control gate connected to the pair of common input/output lines, and a channel connected between one of the bit lines and either one channel of the first and second switching transistors, for carrying out a data input transmission therethrough; and a second pair of input transistors each having a control gate connected to the pair of common input/output lines, and a channel connected between the other one of the bit lines and either one channel of the first and second switching transistors, for carrying out a data input transmission therethrough.
Claim 12
Dependent Claim
32 words
The data transmission circuit as set forth in claim 9, wherein the first and second switching transistors are adapted to turn on in a complementary manner during data inputing and outputing sequence.
Claim 13
Dependent Claim
28 words
The data transmission circuit as set forth in claim 9, wherein the first and second pairs of input transistors are respectively turned on only during data inputing sequence.
Claim 14
Dependent Claim
51 words
The data transmission circuit as set forth in claim 9, wherein when the first switching transistor or the second switching transistor is turned off, a corresponding one of the common input/output lines coupled to a channel of the first or second switching transistor is electrically isolated from the ground voltage node.
Claim 15
Dependent Claim
72 words
The data transmission circuit as set forth in claim 9, further comprising a pair of transmission transistors connected between the respective channel of the first and second switching transistors and either one of the common input/output lines and having each control gate receiving the column selection line signal, and comprising a discharging transistor having a channel connected between the channel of the first and second switching transistors and the ground voltage node.
References Cited (Backward Citations)
US4757215A
Cited
US4984202A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-01-31 | 1997-08-02 | 1998-02-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-01-31 | 2001-08-02 | 2002-02-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-01-31 | 2005-08-02 | 2006-02-01 | $7700.00 | Window Closed / Lapsed |