Patent US5283707A successfully refreshed from Google Patents.
US5283707A
Expired / Lapsed
US
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Inrush current limiting circuit
Assignee: Benhov GmbH LLC
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Filing: 1992-11-27
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Granted: 1994-02-01
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Expires: 2012-11-27
Abstract
Abstract An inrush current limiting circuit includes a power FET switch connected between power source and load and a control circuit. The power FET switch includes one or more parallel-connected power FETs, each having low individual conductive resistances. The control circuit, connected between the power inputs and the gate of power FET switch, includes a voltage supply for providing sufficient voltage to turn the power FET switch on and a time constant circuit for controlling the rate at which the power FET means is turned on. With the voltage supply connected to an optional enable terminal, a DC enable signal can control powering of the load. A second time constant circuit controls the rate of power down.
Inventors
- 👤 Christopher R. Conners
- 👤 Manfred K. Ficker
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 06:11
CPC Classifications
H; H02; H02H; H02H9/00; H02H9/001; Y; Y10; Y10S; Y10S323/00; Y10S323/908
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
148 words
An inrush current limiting circuit, comprising: input terminals for connection to a power supply output and a reference potential; output terminals for connection to a load; power FET means having a control electrode and a conductive controlled path which is connected between the power input terminal and a respective one of the output terminals; voltage supply means connected to the input terminals and having an output for providing sufficient voltage to render the power FET means conductive; first time constant means coupled between the voltage supply means and the control electrode for controlling the rate at which the power FET means is rendered conductive in accordance with a first predetermined time constant; and second time constant means coupled between the control electrode and the reference potential input for controlling the rate at which the power FET means is rendered nonconductive in accordance with a second predetermined time constant.
Claim 2
Dependent Claim
148 words
An inrush current limiting circuit, comprising: input terminals for connection to a power supply output and a reference potential; output terminals for connection to a load; power FET means having a control electrode and a conductive controlled path which is connected between the power input terminal and a respective one of the output terminals; voltage supply means connected to the input terminals and having an output for providing sufficient voltage to render the power FET means conductive; first time constant means coupled between the voltage supply means and the control electrode for controlling the rate at which the power FET means is rendered conductive in accordance with a first predetermined time constant; and second time constant means coupled between the control electrode and the reference potential input for controlling the rate at which the power FET means is rendered nonconductive in accordance with a second predetermined time constant.
Claim 3
Dependent Claim
38 words
A circuit as claimed in claim 1 wherein the first time constant means comprises a resistor connected between the voltage supply means and the control electrode and a capacitor connected between the control electrode and the reference potential.
Claim 4
Dependent Claim
24 words
A circuit as claimed in claim 2 wherein the first time constant has a range of between about 10 ms to about 100 ms.
Claim 5
Dependent Claim
62 words
A circuit as claimed in claim 1 wherein the second time constant means includes a diode, connected in parallel with the resistor of the first time constant means, having an anode connected to the control electrode and a cathode connected to the voltage supply means, and a resistor and a capacitor parallel connected between the anode and the reference potential input terminal.
Claim 6
Dependent Claim
24 words
A circuit as claimed in claim 4 wherein the second time constant has a range of between about 1 ms to about 10 ms.
Claim 7
Dependent Claim
18 words
A circuit as claimed in claim 1 wherein the power FET means includes at least one power FET.
Claim 8
Dependent Claim
17 words
A circuit as claimed in claim 1 wherein the power FET means includes two parallel-connected power FETs.
Claim 9
Dependent Claim
155 words
An inrush current limiting circuit, comprising: input terminals for connection to a power supply output and a reference potential; output terminals for connection to a load; an enable terminal for receiving an enable signal; power FET means having a control electrode and a conductive controlled path which is connected between the power input terminal and a respective one of the output terminals; voltage supply means, connected to the enable terminal and the reference potential input terminal, and having an output for providing sufficient voltage to render the power FET means conductive; first time constant means coupled between the voltage supply means and the control electrode for controlling the rate at which the power FET means is rendered conductive in accordance with a predetermined time constant; and second time constant means coupled between the voltage supply means and the control electrode for rendering the power FET means non-conductive in accordance with a second predetermined time constant.
Claim 10
Dependent Claim
155 words
An inrush current limiting circuit, comprising: input terminals for connection to a power supply output and a reference potential; output terminals for connection to a load; an enable terminal for receiving an enable signal; power FET means having a control electrode and a conductive controlled path which is connected between the power input terminal and a respective one of the output terminals; voltage supply means, connected to the enable terminal and the reference potential input terminal, and having an output for providing sufficient voltage to render the power FET means conductive; first time constant means coupled between the voltage supply means and the control electrode for controlling the rate at which the power FET means is rendered conductive in accordance with a predetermined time constant; and second time constant means coupled between the voltage supply means and the control electrode for rendering the power FET means non-conductive in accordance with a second predetermined time constant.
Claim 11
Dependent Claim
38 words
A circuit as claimed in claim 8 wherein the first time constant means comprises a resistor connected between the voltage supply means and the control electrode and a capacitor connected between the control electrode and the reference potential.
Claim 12
Dependent Claim
24 words
A circuit as claimed in claim 9 wherein the first time constant has a range of between about 10 ms to about 100 ms.
Claim 13
Dependent Claim
58 words
A circuit as claimed in claim 8 wherein the second time constant means includes an NPN transistor having a collector connected to the control electrode, a base coupled to the power supply input terminal, and an emitter connected to the enable terminal and a resistor and capacitor parallel connected between the emitter and the reference potential input terminal.
Claim 14
Dependent Claim
24 words
A circuit as claimed in claim 11 wherein the second time constant has a range of between about 1 ms to about 10 ms.
Claim 15
Dependent Claim
19 words
A circuit as claimed in claim 8 wherein the time power FET means includes at least one power FET.
Claim 16
Dependent Claim
17 words
A circuit as claimed in claim 8 wherein the power FET means includes two parallel-connected power FETs.
Claim 17
Dependent Claim
151 words
An arrangement including a backplane having at least two conductors, a power supply connected to the conductors, and a plurality of circuit cards attached to the backplane and connected to the conductors, each of the plurality of circuit cards including an inrush current limiting circuit comprising: input terminals for connection to the power supply output and a reference potential; output terminals for connection to the load; power FET means having a control electrode and a conductive controlled path which is connected between the power input terminal and a respective one of the output terminals; voltage supply means connected to the input terminals and having an output for providing sufficient voltage to render the power FET means conductive; and time constant means coupled between the voltage supply means and the control electrode for controlling the rate at which the power FET means is rendered conductive in accordance with a predetermined time constant.
Claim 18
Dependent Claim
151 words
An arrangement including a backplane having at least two conductors, a power supply connected to the conductors, and a plurality of circuit cards attached to the backplane and connected to the conductors, each of the plurality of circuit cards including an inrush current limiting circuit comprising: input terminals for connection to the power supply output and a reference potential; output terminals for connection to the load; power FET means having a control electrode and a conductive controlled path which is connected between the power input terminal and a respective one of the output terminals; voltage supply means connected to the input terminals and having an output for providing sufficient voltage to render the power FET means conductive; and time constant means coupled between the voltage supply means and the control electrode for controlling the rate at which the power FET means is rendered conductive in accordance with a predetermined time constant.
Claim 19
Dependent Claim
53 words
A circuit as claimed in claim 15 further comprising an enable terminal for receiving an enable signal and wherein the voltage supply means is connected to the enable terminal and the reference potential input terminal and is responsive to the enable signal for providing sufficient voltage to render the power FET means conductive.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-01-31 | 1997-08-02 | 1998-02-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-01-31 | 2001-08-02 | 2002-02-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-01-31 | 2005-08-02 | 2006-02-01 | $7700.00 | Window Closed / Lapsed |