Analog voltage subtracting circuit and an A/D converter having the subtracting circuit

Claim 2

A subtracting circuit comprising: a) an output terminal for outputting a result of subtraction; b) analog voltage generating means for generating an analog voltage, said analog voltage generating means having i) impedance converting means for converting an analog input signal of a high impedance to an analog output signal of a lower impedance, and ii) offset voltage removing means for removing an offset voltage of said impedance converting means; c) load means having one end connected to said analog voltage generating means and the other end connected to the output terminal; and d) complementary current output means for applying a first current to generate a desired voltage drop at said other end of said load means and applying a second current complementary to said first current to said one end of said load means.

Claim 3

The subtracting circuit according to claim 1, wherein said impedance converting means includes an emitter follower circuit and means coupled between an output node of the emitter follower circuit and the ground terminal for generating a constant current; and said offset voltage removing means includes means for generating a current having the same magnitude as the sum of the first and second currents output from said complementary current output means and a direction opposite thereto.

Claim 4

The subtracting circuit according to claim 1, wherein said impedance converting means includes a transistor, said transistor having its base connected to receive the analog input signal of the high impedance, its collector connected to receive a supply voltage, and its emitter connected to one end of said load means.

Claim 5

The subtracting circuit according to claim 1, wherein said impedance converting means includes a transistor, said transistor having its base connected to receive said analog input signal of high impedance, its collector connected to receive a supply voltage and its emitter connected to one end of said load, and said offset voltage removing means includes means for applying, to one end of said load means, a current corresponding to a difference between the sum of the first and second currents outputted from said complementary current output means and the emitter current of said transistor.

Claim 6

The subtracting circuit according to claim 1, wherein said complementary current output means includes D/A converting means for converting a value A/D-converted by an externally provided A/D converter to an analog signal.

Claim 7

A subtracting circuit comprising: a) an output terminal for outputting a result of subtraction; b) load means having one end connected to said output terminal; c) analog voltage generating means for generating an analog voltage and connected to the other end of said load means, said analog voltage generating means having i) impedance converting mean as for converting an analog input signal of a high impedance to an analog output signal of a lower impedance, and ii) means for drawing out a constant current from one end of said load means for further increasing an offset voltage of said impedance converting means; and d) complementary current output means for applying a first current for generating a desired voltage drop to the other end of said load means and applying a second current complementary to said first current to said one end of said load means.

Claim 8

A subtracting circuit comprising: a) an output terminal for outputting a result of subtraction; b) load means having one end connected to said output terminal; c) analog voltage generating means for generating an analog voltage and connected to the other end of said load means, said analog voltage generating means having i) impedance converting mean as for converting an analog input signal of a high impedance to an analog output signal of a lower impedance, and ii) means for drawing out a constant current from one end of said load means for further increasing an offset voltage of said impedance converting means; and d) complementary current output means for applying a first current for generating a desired voltage drop to the other end of said load means and applying a second current complementary to said first current to said one end of said load means.

Claim 9

A subtracting circuit comprising: an output terminal for outputting a result of subtraction; a load having a first end and a second end connected to the output terminal; complementary current output means for applying a first current to generate a desired voltage drop at said second end of said load and applying a second current complementary to said first current to said first end of said load; analog voltage generating means comprising a transistor having its base connected to receive the analog input signal, its collector connected to a supply voltage node and its emitter connected only to the first end of said load and said complementary current output means; and the sum of the first and second complementary currents being substantially equal to the emitter current of said transistor of said analog voltage generating means.

Claim 10

A subtracting circuit comprising: an output terminal for outputting a result of subtraction; a load having a first end and a second end connected to the output terminal; complementary current output means for applying a first current to generate a desired voltage drop at said second end of said load and applying a second current complementary to said first current to said first end of said load; analog voltage generating means comprising a transistor having its base connected to receive the analog input signal, its collector connected to a supply voltage node and its emitter connected only to the first end of said load and said complementary current output means; and the sum of the first and second complementary currents being substantially equal to the emitter current of said transistor of said analog voltage generating means.

Claim 11

The subtracting circuit of claim 1 further comprising means for applying, to first end of said load, a current corresponding to a difference between the sum of the first and second currents outputted from said complementary current output means and the emitter current of said transistor.

Claim 12

The subtracting circuit of claim 7, wherein said complementary current output means includes D/A converting means for converting a digital signal, produced by an externally provided A/D converter, to an analog signal.

Claim 13

A subtracting circuit coupled to a sample hold circuit of an A/D converter, said subtracting circuit comprising: an output terminal for outputting a result of subtraction; a load having first and second ends, said first end being connected to said output terminal; complementary current output means for applying a first current for generating a desired voltage drop to said first end of said load and applying a second current complementary to said first current to said second end of said load; and a resistor connected between said second end of said load and the sample hold circuit for increasing an offset voltage of the sample hold circuit such that the dynamic range of the A/D converter is shifted.

Claim 14

A subtracting circuit coupled to a sample hold circuit of an A/D converter, said subtracting circuit comprising: an output terminal for outputting a result of subtraction; a load having first and second ends, said first end being connected to said output terminal; complementary current output means for applying a first current for generating a desired voltage drop to said first end of said load and applying a second current complementary to said first current to said second end of said load; and a resistor connected between said second end of said load and the sample hold circuit for increasing an offset voltage of the sample hold circuit such that the dynamic range of the A/D converter is shifted.

Claim 15

An A/D converter for A/D-converting an analog input voltage by dividing the same into upper and lower bits, the A/D converter comprising: a) means for sampling and holding said analog input voltage; b) higher A/D converting means for roughly A/D converting the analog input voltage which has been sampled and held to provide higher bits; c) subtracting means for calculating a difference between said sampled and held analog input voltage and a voltage value corresponding to the higher bits calculated by said higher A/D converting means, said subtracting means having i) an output terminal for outputting a result of subtraction, ii) load means having a first end connected to said sampling and holding means and a second end connected to said output terminal, and iii) complementary current output means for applying a first current to generate a desired voltage drop at said second end of said load means and applying a second current complementary to said first current to said first end of said load means; d) lower A/D converting means, coupled to said output terminal of said subtracting means, for A/D converting the result of subtraction to calculate lower bits; and e) offset voltage removing means, connected to said first end, for removing an offset voltage of impedance converting means.

Claim 16

An A/D converter for A/D-converting an analog input voltage by dividing the same into upper and lower bits, the A/D converter comprising: a) means for sampling and holding said analog input voltage; b) higher A/D converting means for roughly A/D converting the analog input voltage which has been sampled and held to provide higher bits; c) subtracting means for calculating a difference between said sampled and held analog input voltage and a voltage value corresponding to the higher bits calculated by said higher A/D converting means, said subtracting means having i) an output terminal for outputting a result of subtraction, ii) load means having a first end connected to said sampling and holding means and a second end connected to said output terminal, and iii) complementary current output means for applying a first current to generate a desired voltage drop at said second end of said load means and applying a second current complementary to said first current to said first end of said load means; d) lower A/D converting means, coupled to said output terminal of said subtracting means, for A/D converting the result of subtraction to calculate lower bits; and e) offset voltage removing means, connected to said first end, for removing an offset voltage of impedance converting means.

Claim 17

The A/D converter of claim 11, wherein said sampling and holding means includes an emitter follower circuit and means coupled between an output node of the emitter follower circuit and the ground terminal for generating a constant current; and said offset voltage removing means includes means for generating a current having the same magnitude as the sum of the first and second currents output from said complementary current output means and a direction opposite therein.

Claim 18

The A/D converter of claim 11, wherein said sampling and holding means includes a transistor, said transistor having its base connected to receive an analog input signal of the high impedance, its collector connected to receive a supply voltage, and its emitter connected to said first end of said load means.

Claim 19

The A/D converter of claim 11, wherein said sampling and holding means includes a transistor, said transistor having a base connected to receive said analog input signal of high impedance, its collector connected to receive a supply voltage and its emitter connected to said first end of said load means, and said offset voltage removing means includes means for applying, to the first end of said load means, a current corresponding to a difference between the sum of the first and second currents outputted from said complementary current output means and the emitter current of said transistor.

Claim 20

An A/D converter for A/D-converting an analog input voltage by dividing the same into upper and lower bits, the A/D converter comprising: a) means for sampling and holding said analog input voltage and having a transistor with a base, collector and emitter, said base being connected to receive the analog input signal and said collector being connected to a supply voltage node; b) higher A/D converting means for roughly A/D converting the analog input voltage which has been sampled and held to provide higher bits; c) subtracting means for calculating a difference between said sampled and held analog input voltage and a voltage value corresponding to the higher bits calculated by said higher A/D converting means, said subtracting means having i) an output terminal coupled for outputting a result of subtraction, ii) a load having a first end connected to said sampling and holding means and a second end connected to said output terminal, wherein said emitter of said sampling and holding means is only connected to said first end, and iii) complementary current output means for applying a first current to generate a desired voltage drop at said second end of said load means and applying a second current complementary to said first current to said first end of said load, wherein the sum of the first and second complementary currents is substantially equal to the emitter current of said transistor of said sampling and holding means; and d) lower A/D converting means, coupled to said output terminal of said subtracting means, for A/D converting the result of subtraction to calculate lower bits.

Claim 21

An A/D converter for A/D-converting an analog input voltage by dividing the same into upper and lower bits, the A/D converter comprising: a) means for sampling and holding said analog input voltage and having a transistor with a base, collector and emitter, said base being connected to receive the analog input signal and said collector being connected to a supply voltage node; b) higher A/D converting means for roughly A/D converting the analog input voltage which has been sampled and held to provide higher bits; c) subtracting means for calculating a difference between said sampled and held analog input voltage and a voltage value corresponding to the higher bits calculated by said higher A/D converting means, said subtracting means having i) an output terminal coupled for outputting a result of subtraction, ii) a load having a first end connected to said sampling and holding means and a second end connected to said output terminal, wherein said emitter of said sampling and holding means is only connected to said first end, and iii) complementary current output means for applying a first current to generate a desired voltage drop at said second end of said load means and applying a second current complementary to said first current to said first end of said load, wherein the sum of the first and second complementary currents is substantially equal to the emitter current of said transistor of said sampling and holding means; and d) lower A/D converting means, coupled to said output terminal of said subtracting means, for A/D converting the result of subtraction to calculate lower bits.

Claim 22

The A/D converter of claim 15 further comprising means for applying, to said first end of said load, a current corresponding to a difference between the sum of the first and second currents outputted from said complementary current output means and the emitter current of said transistor.

Claim 23

The A/D converter of claim 15, wherein said complementary current output means includes D/A converting means for converting a value A/D-converted by an externally provided A/D converter to an analog signal.