High density power device fabrication process

Claim 1

A method of making a recessed gate field effect power MOS device, the method comprising: forming a substrate (20) including first and second doped layers (24, 26) of first and second opposite dopant polarities to define a body region adjoining an upper surface of the substrate and an underlying drain region; forming a trenching protective layer (30) on the upper surface (28) of the substrate; masking and patterning the trenching protective layer to define an exposed first area (46) and a protected second area of the upper surface of the substrate demarcated by opposite sidewalls of the trenching protective layer; forming sidewall spacers (44) having inner surfaces (48) contacting opposite sidewalls of the trenching protective layer (30) and outer surfaces (47) spaced a predetermined spacing (54) from the sidewalls of the trenching protective layer; forming in the first area (46) of the substrate, between the outer surfaces (47) of the sidewall spacers (44) , a first trench (50) having sidewalls aligned relative to the outer surfaces (47) of the sidewall spacers and extending at least through the layer (26) defining the body region to a bottom wall at least a predetermined depth (56) from the upper surface of the substrate; forming a gate oxide layer (60) on the first trench sidewalls; filling the first trench with polysilicon (62) to a level (64) spaced between the upper surface of the substrate and a top surface of the trenching protective layer (30); applying a protective layer (68) selectively over the polysilicon (62) filled into the first trench, between the sidewall spacers (44) and in contact with the outer surfaces (47) of the sidewall spacers; removing the trenching protective layer to expose the second area of the upper surface (28') of the substrate between the inner surfaces (48) of the sidewall spacers; doping the second area of the upper surface (28') of the substrate between the gate oxide layer (60) on the trench sidewalls with dopant of said second dopant polarity to form a source region (72) atop the body region (26'); forming, in the second area of the substrate (28') between the inner surfaces (48) of the sidewall spacers (44), a second trench (80) having sidewalls aligned relative to the inner surfaces of the sidewall spacers and extending through the layer (72) defining the source region to a bottom wall in the body region (26") of the substrate; and depositing a source conductive layer (94) in the second trench in contact with the source region and the body region; the second trench (80) through the source region and body region defining vertically-oriented source and body layers (86, 90) stacked along the gate oxide layer (60) on opposite sidewalls of the second trench (80) and having a lateral thickness (88) established by the predetermined spacing of the inner and outer surfaces of the sidewall spacers.

Claim 2

A method of making a recessed gate field effect power MOS device, the method comprising: forming a substrate (20) including first and second doped layers (24, 26) of first and second opposite dopant polarities to define a body region adjoining an upper surface of the substrate and an underlying drain region; forming a trenching protective layer (30) on the upper surface (28) of the substrate; masking and patterning the trenching protective layer to define an exposed first area (46) and a protected second area of the upper surface of the substrate demarcated by opposite sidewalls of the trenching protective layer; forming sidewall spacers (44) having inner surfaces (48) contacting opposite sidewalls of the trenching protective layer (30) and outer surfaces (47) spaced a predetermined spacing (54) from the sidewalls of the trenching protective layer; forming in the first area (46) of the substrate, between the outer surfaces (47) of the sidewall spacers (44) , a first trench (50) having sidewalls aligned relative to the outer surfaces (47) of the sidewall spacers and extending at least through the layer (26) defining the body region to a bottom wall at least a predetermined depth (56) from the upper surface of the substrate; forming a gate oxide layer (60) on the first trench sidewalls; filling the first trench with polysilicon (62) to a level (64) spaced between the upper surface of the substrate and a top surface of the trenching protective layer (30); applying a protective layer (68) selectively over the polysilicon (62) filled into the first trench, between the sidewall spacers (44) and in contact with the outer surfaces (47) of the sidewall spacers; removing the trenching protective layer to expose the second area of the upper surface (28') of the substrate between the inner surfaces (48) of the sidewall spacers; doping the second area of the upper surface (28') of the substrate between the gate oxide layer (60) on the trench sidewalls with dopant of said second dopant polarity to form a source region (72) atop the body region (26'); forming, in the second area of the substrate (28') between the inner surfaces (48) of the sidewall spacers (44), a second trench (80) having sidewalls aligned relative to the inner surfaces of the sidewall spacers and extending through the layer (72) defining the source region to a bottom wall in the body region (26") of the substrate; and depositing a source conductive layer (94) in the second trench in contact with the source region and the body region; the second trench (80) through the source region and body region defining vertically-oriented source and body layers (86, 90) stacked along the gate oxide layer (60) on opposite sidewalls of the second trench (80) and having a lateral thickness (88) established by the predetermined spacing of the inner and outer surfaces of the sidewall spacers.