Mask surrogate semiconductor process employing dopant-opaque region

Claim 1

A method, employing no more than one independent mask, of producing an MOS semiconductor device in a substrate structure including a gate oxide layer on an upper surface of a semiconductor substrate, the method comprising: `forming over the gate oxide layer a dopant protective layer; creating a mask-surrogate pattern-definer having a defined outline characteristic in the protective layer; exposing a portion of the upper surface of the substrate within a region bounded by the defined outline characteristic; performing a first coping step to introduce dopant into said exposed upper surface portion of the substrate so as to form a first region of a first conductivity type, opposite a second conductivity type which is the conductivity type of a second region in said substrate, said first region including said exposed under surface of the substrate and extending to a location under peripheral edges of the protective layer providing the defined outline characteristic, said first region being wholly contained in said second region; and after the first doping step, forming a trench in the exposed upper surface of the substrate, the trench being formed to a trench depth greater than a depth of the first region but less than a depth of the second region, and being formed of a width less than a width of the first region such that separated regions of the first conductivity type are provided at sidewalls of the trench, the separated regions constituting source regions of the MOS semiconductor device, the trench sidewalls being formed to protrude laterally toward one another within the trench so that a portion of the silicon substrate containing the first region of said first conductivity type is vertically exposed along the trench sidewalls.

Claim 2

A method, employing no more than one independent mask, of producing an MOS semiconductor device in a substrate structure including a gate oxide layer on an upper surface of a semiconductor substrate, the method comprising: `forming over the gate oxide layer a dopant protective layer; creating a mask-surrogate pattern-definer having a defined outline characteristic in the protective layer; exposing a portion of the upper surface of the substrate within a region bounded by the defined outline characteristic; performing a first coping step to introduce dopant into said exposed upper surface portion of the substrate so as to form a first region of a first conductivity type, opposite a second conductivity type which is the conductivity type of a second region in said substrate, said first region including said exposed under surface of the substrate and extending to a location under peripheral edges of the protective layer providing the defined outline characteristic, said first region being wholly contained in said second region; and after the first doping step, forming a trench in the exposed upper surface of the substrate, the trench being formed to a trench depth greater than a depth of the first region but less than a depth of the second region, and being formed of a width less than a width of the first region such that separated regions of the first conductivity type are provided at sidewalls of the trench, the separated regions constituting source regions of the MOS semiconductor device, the trench sidewalls being formed to protrude laterally toward one another within the trench so that a portion of the silicon substrate containing the first region of said first conductivity type is vertically exposed along the trench sidewalls.

Claim 8

A method employing no more than one independent mask of producing an MOS semiconductor device in a substrate structure including a gate oxide layer on an upper surface of a semiconductor substrate, said method comprising: forming over the gate oxide layer a dopant protective layer; creating a mask-surrogate pattern-definer having a defined outline characteristic in the protective layer; exposing a portion of the upper surface of the substrate within a boundary determined by the defined outline characteristic; forming a trench in the exposed upper surface portion of the substrate, the trench having a base and opposite sidewalls in which a lower substrate surface is exposed, the sidewalls being undercut beneath the gate oxide layer; and simultaneously depositing a gate conductive layer on the oxide layer and a source conductive layer on the lower surface of the substrate, the gate and source conductive layers each conforming to the boundary defined by the defined outline characteristic; the trench being formed to a trench depth and the source conductive layer to a thickness mutually arranged, spacing the source conductive layer below the oxide layer so as to contact the substrate along the sidewalls of the trench and so that the gate and source conductive layers are electrically separated vertically along said boundary.

Claim 9

A method employing no more than one independent mask of producing an MOS semiconductor device in a substrate structure including a gate oxide layer on an upper surface of a semiconductor substrate, said method comprising: forming over the gate oxide layer a dopant protective layer; creating a mask-surrogate pattern-definer having a defined outline characteristic in the protective layer; exposing a portion of the upper surface of the substrate within a boundary determined by the defined outline characteristic; forming a trench in the exposed upper surface portion of the substrate, the trench having a base and opposite sidewalls in which a lower substrate surface is exposed, the sidewalls being undercut beneath the gate oxide layer; and simultaneously depositing a gate conductive layer on the oxide layer and a source conductive layer on the lower surface of the substrate, the gate and source conductive layers each conforming to the boundary defined by the defined outline characteristic; the trench being formed to a trench depth and the source conductive layer to a thickness mutually arranged, spacing the source conductive layer below the oxide layer so as to contact the substrate along the sidewalls of the trench and so that the gate and source conductive layers are electrically separated vertically along said boundary.

Claim 12

A method employing no more than one independent mask of producing an MOS semiconductor device in a substrate structure including a gate oxide layer on an upper surface of a semiconductor substrate, said method comprising: forming over the gate oxide layer a dopant protective layer; creating a mark-surrogate pattern-definer having a defined outline characteristic in the protective layer; exposing a portion of the upper surface of the substrate within a boundary determined by the defined outline characteristic; forming a trench in the exposed upper surface portion of the substrate, the trench having a base and opposite sidewalls in which a lower substrate surface is exposed and the trench sidewalls are inclined toward one another in a depthwise direction; and simultaneously depositing a gate conductive layer on the oxide layer and a source conductive layer on the lower surface of the substrate, the gate and source conductive layers each conforming to the boundary defined by the defined outline characteristic; the trench being formed to a trench depth and the source conductive layer to a thickness mutually arranged, spacing the source conductive layer below the oxide layer so as to contact the substrate along the sidewalls of the trench and so that the gate and source conductive layers are electrically separated vertically along said boundary.

Claim 13

A method employing no more than one independent mask of producing an MOS semiconductor device in a substrate structure including a gate oxide layer on an upper surface of a semiconductor substrate, said method comprising: forming over the gate oxide layer a dopant protective layer; creating a mark-surrogate pattern-definer having a defined outline characteristic in the protective layer; exposing a portion of the upper surface of the substrate within a boundary determined by the defined outline characteristic; forming a trench in the exposed upper surface portion of the substrate, the trench having a base and opposite sidewalls in which a lower substrate surface is exposed and the trench sidewalls are inclined toward one another in a depthwise direction; and simultaneously depositing a gate conductive layer on the oxide layer and a source conductive layer on the lower surface of the substrate, the gate and source conductive layers each conforming to the boundary defined by the defined outline characteristic; the trench being formed to a trench depth and the source conductive layer to a thickness mutually arranged, spacing the source conductive layer below the oxide layer so as to contact the substrate along the sidewalls of the trench and so that the gate and source conductive layers are electrically separated vertically along said boundary.

Claim 16

A method employing no more than one independent mask of producing an MOS semiconductor device in a substrate structure including a gate oxide layer on an upper surface of a semiconductor substrate, said method comprising: forming over the gate oxide layer a polysilicon dopant protective layer; creating a mask-surrogate pattern-definer having a defined outline characteristic in the protective layer; exposing a portion of the upper surface of the substrate within a boundary determined by the defined outline characteristic; forming a trench in the exposed upper surface portion of the substrate, the trench having a base and opposite sidewalls in which a lower substrate surface is exposed; reducing the thickness of the polysilicon layer; and simultaneously depositing a gate conductive layer on the oxide layer and a source conductive layer on the lower surface of the substrate, the gate and source conductive layers each conforming to the boundary defined by the defined outline characteristic; the trench being formed to a trench depth and the source conductive layer to a thickness mutually arranged, spacing the source conductive layer below the oxide layer so as to contact the substrate along the sidewalls of the trench and so that the gate and source conductive layers are electrically separated vertically along said boundary.

Claim 17

A method employing no more than one independent mask of producing an MOS semiconductor device in a substrate structure including a gate oxide layer on an upper surface of a semiconductor substrate, said method comprising: forming over the gate oxide layer a polysilicon dopant protective layer; creating a mask-surrogate pattern-definer having a defined outline characteristic in the protective layer; exposing a portion of the upper surface of the substrate within a boundary determined by the defined outline characteristic; forming a trench in the exposed upper surface portion of the substrate, the trench having a base and opposite sidewalls in which a lower substrate surface is exposed; reducing the thickness of the polysilicon layer; and simultaneously depositing a gate conductive layer on the oxide layer and a source conductive layer on the lower surface of the substrate, the gate and source conductive layers each conforming to the boundary defined by the defined outline characteristic; the trench being formed to a trench depth and the source conductive layer to a thickness mutually arranged, spacing the source conductive layer below the oxide layer so as to contact the substrate along the sidewalls of the trench and so that the gate and source conductive layers are electrically separated vertically along said boundary.

Claim 18

A method employing no more than one independent mask of producing an MOS semiconductor device in a substrate structure including a gate oxide layer on an upper surface of a semiconductor substrate, said method comprising: forming over the gate oxide layer a dopant protective layer; creating a mask-surrogate pattern-definer having a defined outline characteristic in the protective layer; exposing a portion of the upper surface of the substrate within a boundary determined by the defined outline characteristic; forming a trench in the exposed upper surface portion of the substrate, the trench having a base and opposite sidewalls in which a lower substrate surface is exposed; and simultaneously depositing a gate conductive layer on the oxide layer and a source conductive layer on the lower surface of the substrate, the gate and source conductive layers each conforming to the boundary defined by the defined outline characteristic; the trench being formed to a trench depth and the source conductive layer to a thickness mutually arranged, spacing the source conductive layer below the oxide layer so as to contact the substrate along the sidewalls of the trench and so that the gate and source conductive layers are electrically separated vertically along said boundary, the trench sidewalls being formed to protrude laterally toward one another within the trench so that a portion of the silicon substrate containing a first region of a first conductivity type is vertically exposed along each of the trench sidewalls.

Claim 19

A method employing no more than one independent mask of producing an MOS semiconductor device in a substrate structure including a gate oxide layer on an upper surface of a semiconductor substrate, said method comprising: forming over the gate oxide layer a dopant protective layer; creating a mask-surrogate pattern-definer having a defined outline characteristic in the protective layer; exposing a portion of the upper surface of the substrate within a boundary determined by the defined outline characteristic; forming a trench in the exposed upper surface portion of the substrate, the trench having a base and opposite sidewalls in which a lower substrate surface is exposed; and simultaneously depositing a gate conductive layer on the oxide layer and a source conductive layer on the lower surface of the substrate, the gate and source conductive layers each conforming to the boundary defined by the defined outline characteristic; the trench being formed to a trench depth and the source conductive layer to a thickness mutually arranged, spacing the source conductive layer below the oxide layer so as to contact the substrate along the sidewalls of the trench and so that the gate and source conductive layers are electrically separated vertically along said boundary, the trench sidewalls being formed to protrude laterally toward one another within the trench so that a portion of the silicon substrate containing a first region of a first conductivity type is vertically exposed along each of the trench sidewalls.