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US5282165A
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Random access memory with redundancy repair circuit
Assignee: Panasonic Holdings Corp
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Filing: 1991-05-08
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Granted: 1994-01-25
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Expires: 2011-05-08
Abstract
Abstract A random access memory includes a redundancy repair circuit having a plurality of parallel connected transistors and a plurality of fuses connected to respective drains of the plurality of transistors. An electrically resistive element is connected to a common node to reduce a difference in operating speeds between a first case in which the circuit is precharged from a state in which discharge to a low level was effected via one of the transistors and a case in which precharging of the circuit is effected from a state in which discharging was carried out via a plurality of the transistors.
Inventors
- 👤 Naomi Miyake
- 👤 Tatsumi Sumi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 19:55
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C29/84
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
118 words
A random access memory including a redundancy repair circuit for replacing a defective memory cell with a spare memory cell, said redundancy repair circuit comprising: a plurality of transistors, connected to each other in parallel, each having a source, a drain and a gate, wherein each source of said plurality of transistors is connected to a common node, and wherein each gate of said plurality of transistors receives an address signal transmitted within said random access memory; a plurality of fuses, which are selectively opened to store an address of said defective memory cell, respectively connected to said drains of said plurality of transistors; and, an electrically resistive element connected between said common node and a ground line.
Claim 2
Dependent Claim
118 words
A random access memory including a redundancy repair circuit for replacing a defective memory cell with a spare memory cell, said redundancy repair circuit comprising: a plurality of transistors, connected to each other in parallel, each having a source, a drain and a gate, wherein each source of said plurality of transistors is connected to a common node, and wherein each gate of said plurality of transistors receives an address signal transmitted within said random access memory; a plurality of fuses, which are selectively opened to store an address of said defective memory cell, respectively connected to said drains of said plurality of transistors; and, an electrically resistive element connected between said common node and a ground line.
Claim 3
Dependent Claim
32 words
A random access memory as claimed in claim 1, wherein said electrically resistive element is a transistor having a gate which receives a control signal for controlling a resistance of said transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-01-24 | 1997-07-26 | 1998-01-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-01-24 | 2001-07-26 | 2002-01-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-01-24 | 2005-07-26 | 2006-01-25 | $7700.00 | Window Closed / Lapsed |