Leading one anticipator and floating point addition/subtraction apparatus employing same

Claim 2

Apparatus for identifying a limited number of positions within a result of a floating point operation, wherein a leading 1 or 0 is located in one of the positions, said apparatus suitable for use in a leading one anticipator of an operation apparatus, and comprising: subtraction means for performing a subtraction with respect to a binary minuend having i digits and a binary subtrahend having j digits to generate a redundant binary numeral Zsd having "-1", "0" or "1" at each digit thereof, each of said i and j being an integer; a plurality of intermediate-carry/intermediate-sum generating (ICISG) means coupled to the subtraction means, each ICISG means generating anintermediate carry C k and an intermediate sum S k in accordance with Zsd k =2C k +S k by use of a redundant binary numeral Zsd k positioned at a kth digit from a least significant digit of said redundant binary numeral Zsd and a redundant binary numeral Zsd k+1 positioned at a (k+1)th digit from said least significant digit so that C k =Zsd k when Zsd k+1 ="1" or "1" and C k =0 when Zsd k+1 ="0", said k being an integer; and a plurality of circuits, each coupled to a respective ICISG means, each circuit generating a signal Z k so that said signal Z k indicates a first numeral when a result of an addition with respect to an intermediate carry C k-1 transferred from a next-lower order digit and said intermediate sum S k is "0" and said signal Z k indicates a second number when said result of the addition is a numeral other than "0", a position of a leading second numeral indicated by said signal Z k indicating one of a same digit position as a leading significant digit position of a result obtained by said operation apparatus and a digit position one digit above said leading significant digit position.

Claim 3

Apparatus for identifying a limited number of positions within a result of a floating point operation, wherein a leading 1 or 0 is located in one of the positions, said apparatus suitable for use in a leading one anticipate of an operation apparatus, and comprising: a plurality of leading 1/0 detectors, each of which comprises: three OR type gates positioned at a first stage; two OR type gates positioned at a second stage; and an AND-NOR gate positioned at a third stage, wherein, a binary numeral X k is inputted into first and second OR type gates of the first stage whereas a binary numeral Y k is inputted into first and third OR type gates of the first stage, wherein said second and third OR type gates of the first stage also receive a binary numeral X k-1 transferred from a next-lower-order digit and a binary numeral Y k-1 transferred from the next-lower-order digit, respectively, wherein an output from said second OR type gate of the first stage and that from said third OR type gate of the first stage are inputted into first and second OR type gates of the second stage, respectively, and an output from a first OR type gate of a first stage of a next-higher-order digit is inputted into said first and second OR type gates of the second stage, and wherein an output from said first OR type gate of the first stage, that from said first OR type gate of the second stage, and that from said second OR type gate of the second stage are inputted into said AND-NOR gate, and said AND-OR gate outputs a binary numeral Z k , each of said X k , said Y k , and said Z k being a binary numeral positioned at a kth digit, said k being an integer.

Claim 4

Apparatus for identifying a limited number of positions within a result of a floating point operation, wherein a leading 1 or 0 is located in one of the positions, said apparatus suitable for use in a leading one anticipate of an operation apparatus, and comprising: a plurality of leading 1/0 detectors, each of which comprises: three OR type gates positioned at a first stage; two OR type gates positioned at a second stage; and an AND-NOR gate positioned at a third stage, wherein, a binary numeral X k is inputted into first and second OR type gates of the first stage whereas a binary numeral Y k is inputted into first and third OR type gates of the first stage, wherein said second and third OR type gates of the first stage also receive a binary numeral X k-1 transferred from a next-lower-order digit and a binary numeral Y k-1 transferred from the next-lower-order digit, respectively, wherein an output from said second OR type gate of the first stage and that from said third OR type gate of the first stage are inputted into first and second OR type gates of the second stage, respectively, and an output from a first OR type gate of a first stage of a next-higher-order digit is inputted into said first and second OR type gates of the second stage, and wherein an output from said first OR type gate of the first stage, that from said first OR type gate of the second stage, and that from said second OR type gate of the second stage are inputted into said AND-NOR gate, and said AND-OR gate outputs a binary numeral Z k , each of said X k , said Y k , and said Z k being a binary numeral positioned at a kth digit, said k being an integer.

Claim 5

The apparatus according to claim 2, wherein said first OR type gate of the first stage is an EX-NOR gate.

Claim 6

The apparatus according to claim 3, wherein each of said second and third OR type gates of the first stage is an EX-NOR gate whereas each of said OR type gates of the second stage is an EX-OR gate.

Claim 7

The apparatus according to claim 3, wherein each of said second and third OR type gates of the first stage is an EX-OR gate whereas each of said OR type gates of the second stage is an EX-NOR gate.

Claim 8

The apparatus according to claim 3, wherein each of said second OR type gate of the first stage and said second OR type gate of the second stage is an EX-NOR gate whereas each of said third OR type gate of the first stage and said first OR type gate of the second stage is an EX-OR gate.

Claim 9

The apparatus according to claim 3, wherein each of said second OR type gate of the first stage and said second OR type gate of the second stage is an EX-OR gate whereas each of said third OR type gate of the first stage and said first OR type gate of the second stage is an EX-NOR gate.

Claim 10

A floating point addition/subtraction apparatus for performing an addition or subtraction with respect to two floating point operands each having a mantissa operand, an exponent operand, and a sign operand, said apparatus comprising: an adder/subtractor for performing an addition or subtraction with respect to the mantissa operands of said two operands after an digit alignment processing; leading one anticipator means comprising: A subtraction means for performing a subtraction with respect to a binary minuend having i digits and a binary subtrahend having j digits to generate a redundant binary numeral Zsd having "-1", "0 " or "1" at each digit thereof, each of said i and j being an integer, a plurality of intermediate-carry/intermediate-sum generating (ICISG) means coupled to the subtraction means, each ICISG means generating an intermediate carry C k and an intermediate sum S k in accordance with Zsd k =2C k +S k by use of a redundant binary numeral Zsd k positioned at a k th digit from a least significant digit of said redundant binary numeral Zsd and a redundant binary numeral Zsd k+1 positioned at a (k+1) th digit from said least significant digit so that C k =Zsd k when Zsd k+1 ="1" or "-1" and C k =0 when Zsd k+1 ="0", said k being an integer, and a plurality of addition means, each coupled to a respective ICISG means, each addition means generating a signal Z k so that said signal Z k indicates a first numeral when a result of an addition with respect to an intermediate carry C k-1 transferred from a next-lower-order digit and said intermediate sum S k is "0" and said signal Z k indicates a second numeral when said result of the addition is a numeral other than "0", a position of a leading second numeral indicated by said signal Z k indicating one of a same digit position as a leading significant digit position of a result obtained by said adder/subtractor and a digit position one digit upper than said leading significant digit position; a priority encoder for receiving said signal Z k from said leading one anticipator means to determine the number of non-significant digits from a most significant digit, and for producing an output signal therefrom identifying a shift value; a left barrel shifter for receiving the output signal of the priority encoder and a result of a subtraction performed by said adder/subtracter, and for shifting said result of the subtraction left according to the output signal of the priority encoder to form a normalized result; and an alignment circuit for shifting the normalized result left by an additional digit if the normalized result has a leading zero; whereby a normalization processing is performed in parallel with an addition or subtraction of the mantissa parts of said minuend and subtrahend.

Claim 11

A floating point addition/subtraction apparatus for performing an addition or subtraction with respect to two floating point operands each having a mantissa operand, an exponent operand, and a sign operand, said apparatus comprising: an adder/subtractor for performing an addition or subtraction with respect to the mantissa operands of said two operands after an digit alignment processing; leading one anticipator means comprising: A subtraction means for performing a subtraction with respect to a binary minuend having i digits and a binary subtrahend having j digits to generate a redundant binary numeral Zsd having "-1", "0 " or "1" at each digit thereof, each of said i and j being an integer, a plurality of intermediate-carry/intermediate-sum generating (ICISG) means coupled to the subtraction means, each ICISG means generating an intermediate carry C k and an intermediate sum S k in accordance with Zsd k =2C k +S k by use of a redundant binary numeral Zsd k positioned at a k th digit from a least significant digit of said redundant binary numeral Zsd and a redundant binary numeral Zsd k+1 positioned at a (k+1) th digit from said least significant digit so that C k =Zsd k when Zsd k+1 ="1" or "-1" and C k =0 when Zsd k+1 ="0", said k being an integer, and a plurality of addition means, each coupled to a respective ICISG means, each addition means generating a signal Z k so that said signal Z k indicates a first numeral when a result of an addition with respect to an intermediate carry C k-1 transferred from a next-lower-order digit and said intermediate sum S k is "0" and said signal Z k indicates a second numeral when said result of the addition is a numeral other than "0", a position of a leading second numeral indicated by said signal Z k indicating one of a same digit position as a leading significant digit position of a result obtained by said adder/subtractor and a digit position one digit upper than said leading significant digit position; a priority encoder for receiving said signal Z k from said leading one anticipator means to determine the number of non-significant digits from a most significant digit, and for producing an output signal therefrom identifying a shift value; a left barrel shifter for receiving the output signal of the priority encoder and a result of a subtraction performed by said adder/subtracter, and for shifting said result of the subtraction left according to the output signal of the priority encoder to form a normalized result; and an alignment circuit for shifting the normalized result left by an additional digit if the normalized result has a leading zero; whereby a normalization processing is performed in parallel with an addition or subtraction of the mantissa parts of said minuend and subtrahend.