High-speed semicondustor memory integrated circuit arrangement having power and signal lines with reduced resistance

Claim 1

A semiconductor integrated circuit comprising: a plurality of memory blocks, each memory block having a substantially rectangular form and including dynamic memory cells and sense amplifiers; and a main power-source line for supplying a power-source voltage to said sense amplifiers of said plurality of memory blocks, wherein said plurality of memory blocks are arrayed along a first direction, wherein in each of said memory blocks said sense amplifiers are disposed along a second direction which is substantially perpendicular to said first direction, wherein in each of said memory blocks said dynamic memory cells are disposed along said first direction as well as said second direction, and in each of said memory blocks those ones of said dynamic memory cells which are arrayed in said first direction and which are coupled to an associated one of said sense amplifiers, via a respectively associated pair of data lines, comprise a respective group of said dynamic memory cells, wherein in said plurality of memory blocks said main power-source line is disposed along said first direction, wherein in each of said memory blocks a subsidiary power-source line coupled to said main power-source line is disposed along said second direction, wherein in each of said memory blocks a plurality of switching means are coupled between said subsidiary power-source line and said sense amplifiers, respectively, and are disposed along said second direction, and wherein said plurality of switching means, disposed along said second direction in each of said memory blocks, are controlled by a respectively associated selection signal so that sense amplifiers in one of said memory blocks can be activated while sense amplifiers in remaining ones of said memory blocks remain inactive.