Floating gate nonvolatile memory with configurable erasure blocks

Claim 2

A nonvolatile memory device residing on a substrate, comprising: (A) a first block comprising a first memory cell, a first bit line coupled to a drain of the first memory cell, and a first source line coupled to a source of the first memory cell; (B) a second block comprising a second memory cell, a second bit line coupled to a drain of the second memory cell, and a second source line coupled to a source of the second memory cell; (C) a word line coupled to control gates of the first and second memory cells; (D) first source switch means coupled to the first source line for selectively coupling a first potential, a second potential, and a third potential to the first source line, wherein the second potential has a voltage intermediate between the first potential and the third potential; (E) second source switch means coupled to the second source line for selectively coupling one of the first, second, and third potentials to the second source line; (F) block select means for selecting one the first and second source switch means to couple one of the first, second, and third potentials to its respective one of the first and second source lines, wherein the block select means receives a block address for selecting one of the first and second source switch means; and (G) configuration cell means coupled to the block select means for configuring block operations of the first and second blocks, wherein the configuration cell means can be in a first voltage state and a second voltage state, wherein when the configuration cell means is in the first voltage state, the configuration cell means causes the block select means to separately select one of the first and second source switch means depending upon the address received, wherein when the configuration cell means is in the second voltage state, the configuration cell means causes the block select means to collectively select the first and second source switch means.

Claim 3

The nonvolatile memory device of claim 1, further comprising a plurality of blocks, each associated with one of a plurality of source switches, wherein the plurality of source switches are coupled to the block select means, wherein the configuration cell means causes the block select means to separately select one of the plurality of source switches depending upon the address received when the configuration cell means is in the first voltage state, wherein the configuration cell means causes the block select means to collectively select a number of the plurality of source switches depending upon the address received when the configuration cell means is in the second voltage state.

Claim 4

The nonvolatile memory device of claim 2, wherein the configuration cell means further comprises a plurality of configuration cells, each can be in the first voltage state and the second voltage state.

Claim 5

The nonvolatile memory device of claim 1, wherein the first block includes a first sub-block and a second sub-block, wherein the second block includes a third sub-block and a fourth sub-block.

Claim 6

The nonvolatile memory device of claim 4, wherein the first source switch means comprises a first source switch coupled to the first sub-block and a second source switch coupled to the second sub-block, wherein the second source switch means comprises a third source switch coupled to the third sub-block and a fourth source switch coupled to the fourth sub-block.

Claim 7

The nonvolatile memory device of claim 5, wherein the first sub-block of the first block is grouped together with the third sub-block of the second block on the substrate and the second sub-block of the first block is grouped together with the fourth sub-block of the second block on the substrate.

Claim 8

The nonvolatile memory device of claim 1, wherein the nonvolatile memory device is an electrically programmable and electrically erasable read only memory device.

Claim 9

The nonvolatile memory device of claim 1, wherein the configuration cell means comprises a content addressable memory cell.

Claim 10

The nonvolatile memory device of claim 1, wherein the configuration cell means can be electrically erased and programmed to reconfigure the block operations of the first and second blocks.

Claim 11

The nonvolatile memory device of claim 1, further comprising means for disabling the configuration cell means to configure the block operation of the first and second blocks during a read operation and a programming operation.

Claim 12

A nonvolatile memory device residing on a substrate, comprising: (A) a first block that comprises (a) a first sub-block associated with a first data pin of the memory device, comprising (1) a first memory cell; (2) a first bit line coupled to a drain of the first memory cell; (3) a first source line coupled to a source of the first memory cell; (b) a second sub-block associated with a second data pin of the memory device, comprises (1) a second memory cell; (2) a second bit line coupled to a drain of the second memory cell; (3) a second source line coupled to a source of the second memory cell; (B) a second block that comprises (a) a third sub-block associated with the first data pin, comprising (1) a third memory cell; (2) a third bit line coupled to a drain of the third memory cell; (3) a third source line coupled to a source of the third memory cell; (b) a fourth sub-block associated with the second data pin, comprising (1) a fourth memory cell; (2) a fourth bit line coupled to a drain of the fourth memory cell; (3) a fourth source line coupled to a source of the fourth memory cell, wherein the first sub-block of the first block and the third sub-block of the second block are grouped together on the substrate to form a first data bit group corresponding to the first data pin, wherein the second sub-block of the first block and the fourth sub-block of the second block are grouped together on the substrate to form a second data bit group corresponding to the second data pin; (C) a word line coupled to control gates of the first, second, third, and fourth memory cells; (D) first source switch means coupled to the first source line of the first sub-block and to the second source line of the second sub-block for selectively coupling a first potential, a second potential, and a third potential to the first and second source lines, wherein the second potential has a voltage intermediate between the first potential and the third potential; (E) second source switch means coupled to the third source line of the third sub-block and to the fourth source line of the fourth sub-block for selectively coupling one of the first, second, and third potentials to the third and fourth source lines; (F) block select means for selecting one of the first and second source switch means to couple one of the first, second, and third potentials to its respective ones of the first, second, third, and fourth source lines, wherein the block select means receives a block address for selecting one of the first and second source switch means; and (G) configuration cell means coupled to the block select means for configuring block operations of the first and second blocks, wherein the configuration cell means can be in a first voltage state and a second voltage state, wherein when the configuration cell means is in the first voltage state, the configuration cell means causes the block select means to separately select one of the first and second source switch means depending upon the address received, wherein when the configuration cell means is in the second voltage state, the configuration cell means causes the block select means to collectively select the first and second source switch means.

Claim 13

A nonvolatile memory device residing on a substrate, comprising: (A) a first block that comprises (a) a first sub-block associated with a first data pin of the memory device, comprising (1) a first memory cell; (2) a first bit line coupled to a drain of the first memory cell; (3) a first source line coupled to a source of the first memory cell; (b) a second sub-block associated with a second data pin of the memory device, comprises (1) a second memory cell; (2) a second bit line coupled to a drain of the second memory cell; (3) a second source line coupled to a source of the second memory cell; (B) a second block that comprises (a) a third sub-block associated with the first data pin, comprising (1) a third memory cell; (2) a third bit line coupled to a drain of the third memory cell; (3) a third source line coupled to a source of the third memory cell; (b) a fourth sub-block associated with the second data pin, comprising (1) a fourth memory cell; (2) a fourth bit line coupled to a drain of the fourth memory cell; (3) a fourth source line coupled to a source of the fourth memory cell, wherein the first sub-block of the first block and the third sub-block of the second block are grouped together on the substrate to form a first data bit group corresponding to the first data pin, wherein the second sub-block of the first block and the fourth sub-block of the second block are grouped together on the substrate to form a second data bit group corresponding to the second data pin; (C) a word line coupled to control gates of the first, second, third, and fourth memory cells; (D) first source switch means coupled to the first source line of the first sub-block and to the second source line of the second sub-block for selectively coupling a first potential, a second potential, and a third potential to the first and second source lines, wherein the second potential has a voltage intermediate between the first potential and the third potential; (E) second source switch means coupled to the third source line of the third sub-block and to the fourth source line of the fourth sub-block for selectively coupling one of the first, second, and third potentials to the third and fourth source lines; (F) block select means for selecting one of the first and second source switch means to couple one of the first, second, and third potentials to its respective ones of the first, second, third, and fourth source lines, wherein the block select means receives a block address for selecting one of the first and second source switch means; and (G) configuration cell means coupled to the block select means for configuring block operations of the first and second blocks, wherein the configuration cell means can be in a first voltage state and a second voltage state, wherein when the configuration cell means is in the first voltage state, the configuration cell means causes the block select means to separately select one of the first and second source switch means depending upon the address received, wherein when the configuration cell means is in the second voltage state, the configuration cell means causes the block select means to collectively select the first and second source switch means.

Claim 14

The nonvolatile memory device of claim 11, wherein the first source switch means comprises a first source switch coupled to the first source line of the first sub-block and a second source switch coupled to the second source line of the second sub-block, wherein the second source switch means comprises a third source switch coupled to the third source line of the third sub-block and a fourth source switch coupled to the fourth source line of the fourth sub-block.

Claim 15

The nonvolatile memory device of claim 11, further comprising (i) first sensing means coupled to the first and third bit lines of the first data bit group for detecting a first voltage level on a selected one of the first and third bit lines and for applying the detected first voltage level to the first data pin; and (ii) second sensing means coupled to the second and fourth bit lines of the second data bit group for detecting a second voltage level on a selected one of the second and fourth bit lines and for applying the detected second voltage level to the second data pin.

Claim 16

The nonvolatile memory device of claim 11, further comprising a plurality of data bit groups, each being associated with one of a plurality of data pins of the memory device, and a plurality of blocks, each having a plurality of sub-blocks and each associated with one of a plurality of source switch means, wherein each of the plurality of data bit groups includes one of the plurality of sub-blocks of each of the plurality of blocks, wherein the plurality of source switch means are coupled to the block select means, wherein the configuration cell means causes the block select means to separately select one of the plurality of source switch means depending upon the address received when the configuration cell means is in the first voltage state, wherein the configuration cell means causes the block select means to collectively select a number of the plurality of source switch means depending upon the address received when the configuration cell means is in the second voltage state.

Claim 17

The nonvolatile memory device of claim 14, wherein the configuration cell means further comprises a plurality of configuration cells, each can be in the first voltage state and the second voltage state.

Claim 18

The nonvolatile memory device of claim 14, wherein each of the plurality of source switch circuits further comprises a plurality of source switches, each associated with one of the plurality of sub-blocks of each of the plurality of blocks.

Claim 19

The nonvolatile memory device of claim 11, wherein the configuration cell means comprises a content addressable memory cell.

Claim 20

The nonvolatile memory device of claim 11, wherein the nonvolatile memory device is an electrically programmable and electrically erasable read only memory device.

Claim 21

The nonvolatile memory device of claim 11, wherein the configuration cell means can be electrically erased and programmed to reconfigure the block operations of the first and second blocks.

Claim 22

The nonvolatile memory device of claim 11, further comprising means for disabling the configuration cell means to configure the block operations of the first and second blocks during a read operation and a programming operation.