Method for testing semiconductor integrated circuits soldered to boards and use of a transistor tester for this method

Claim 1

A method of testing an integrated circuit comprising the steps of determining the existence of parasitic transistors in an integrated circuit of a first type while the integrated circuit is unattached to a circuit board by ascertaining diode characteristics of combinations of two pins at a time, connecting a transistor tester to selected pins of the integrated circuit, applying a voltage across the pins of an integrated circuit of said first type with the transistor tester while said integrated circuit is soldered to a circuit board, measuring the currents resulting from the voltage applied across the pins of the integrated circuit, and determining from the measured currents control characteristics of a parasitic transistor of the integrated circuit using the tester.

Claim 2

A method of testing an integrated circuit comprising the steps of determining the existence of parasitic transistors in an integrated circuit of a first type while the integrated circuit is unattached to a circuit board by ascertaining diode characteristics of combinations of two pins at a time, connecting a transistor tester to selected pins of the integrated circuit, applying a voltage across the pins of an integrated circuit of said first type with the transistor tester while said integrated circuit is soldered to a circuit board, measuring the currents resulting from the voltage applied across the pins of the integrated circuit, and determining from the measured currents control characteristics of a parasitic transistor of the integrated circuit using the tester.

Claim 3

A method for testing a semiconductor integrated circuit having a plurality of pins soldered to a circuit board comprising the steps of selecting a set of three pins of the integrated circuit of which one is a ground pin of the integrated circuit and the other two are non-ground pins, connecting a non-ground pin of said set to a ground connection of a transistor tester, connecting the other non-ground pin of the set to a first output of the tester providing a first voltage, the first voltage being selected to draw current from the collector of a conducting transistor, connecting the ground pin of the set to a second output of the tester delivering a second voltage, the second voltage being of a value selected to cause a transistor to become conductive when applied between its base and emitter electrodes, and determining whether the part of the integrated circuit connected to the set of selected pins of the integrated circuit responds to the voltages in the way a conductive transistor would respond.

Claim 4

A method for testing a semiconductor integrated circuit having a plurality of pins soldered to a circuit board comprising the steps of selecting a set of three pins of the integrated circuit of which one is a ground pin of the integrated circuit and the other two are non-ground pins, connecting a non-ground pin of said set to a ground connection of a transistor tester, connecting the other non-ground pin of the set to a first output of the tester providing a first voltage, the first voltage being selected to draw current from the collector of a conducting transistor, connecting the ground pin of the set to a second output of the tester delivering a second voltage, the second voltage being of a value selected to cause a transistor to become conductive when applied between its base and emitter electrodes, and determining whether the part of the integrated circuit connected to the set of selected pins of the integrated circuit responds to the voltages in the way a conductive transistor would respond.