Method for identification of parasitic transistor devices in an integrated structure

Claim 2

A high voltage nodal method for identifying undesirable parasitic transistors in an integrated circuit design layout during the computer-aided design of an integrated circuit, said computer-aided design including a computer system with peripheral devices for accepting and storing a circuit's design data and executing commercially available computer-aided circuit analysis and circuit physical layout software programs according to said circuit design data, said peripheral devices including a terminal graphical display device, said method comprising the steps of: (a) executing a circuit analysis run on said stored circuit design data using said provided computer-aided circuit analysis software program; (b) creating a high voltage output data file according to said executed circuit analysis run, wherein the only information contained is circuit nodal information concerning whether a node voltage value is greater than a set high voltage value; (c) laying out a physical circuit design structure according to said stored circuit design data using said provided computer-aided circuit physical layout software program; (d) creating a physical design output data file according to said layed out physical circuit design structure wherein all circuit node locations are identified; (e) merging said created high voltage and physical design output data files; (f) creating a physical design input data file from said merging step, wherein, portions of said layed out physical circuit design structure, having nodes corresponding to a high voltage node, are idnetified; (g) inputting said physical design input data file to said computer system with said provided computer-aided circuit physical layout software program; (h) displaying on said graphical display device all circuit design structure corresponding to said physical design input data file, said display showing all suspect parasitic transistor regions in said circuit design structure; and (i) identifying, from said displaying step of said suspect parasitic transistor regions in said circuit design structure, all undesirable parasitic transistors.

Claim 3

A high voltage nodal method for identifying undesirable parasitic transistors in an integrated circuit design layout during the computer-aided design of an integrated circuit, as recited in claim 1 wherein: said step of creating a high voltage output data file includes providing input operating conditions and identification of the circuit nodes.

Claim 4

A high voltage nodal method for identifying undesirable parasitic transistors in an integrated circuit design layout during the computer-aided design of an integrated circuit, as recited in claim 1 wherein: said step of displaying on said graphical display device all circuit design structure corresponding to said physical design input data file includes displaying pre-selected structures in a semiconductor epitaxial region capable of interacting with the structure to create said undesired parasitic transistors.

Claim 5

A high voltage nodal method for identifying undesirable parasitic transistors in an integrated circuit design layout during the computer-aided design of an integrated circuit, as recited in claim 3 wherein: said step of displaying pre-selected structures in a semiconductor epitaxial region includes identifying and displaying epitaxial regions in which a high voltage P-diffused region is not protected from low voltage regions such as low voltage P-diffused regions and low voltage overlying metallic region.

Claim 6

A high voltage nodal method for identifying undesirable parasitic transistors in an integrated circuit design layout during the computer-aided design of an integrated circuit, as recited in claim 4 wherein: said step of displaying includes highlighting epitaxial regions having an undesirable parasitic transistor configuration.

Claim 7

A high voltage nodal method for identifying undesirable parasitic transistors in an integrated circuit design layout during the computer-aided design of an integrated circuit, said computer-aided design including a computer system with peripheral devices for accepting and storing a circuit's design data and executing commercially available computer-aided circuit analysis and circuit physical layout software programs according to said circuit design data, said peripheral devices including a terminal graphical display device, said method comprising the steps of: (a) providing design data for a circuit being designed in an integrated circuit design manner, said step of providing design data includes providing input operating conditions, a reference high voltage value for comparison purposes and identification of the circuit nodes; (b) inputting said circuit design data into said computer system for storage into a designated design data file; (c) executing a circuit analysis run on said stored circuit design data using said provided computer-aided circuit analysis software program; (d) creating a high voltage output data file according to said executed circuit analysis run, wherein the only information contained is circuit nodal information concerning whether a node voltage value is greater than said reference high voltage value; (e) laying out a physical circuit design structure according to said stored circuit design data using said provided computer-aided circuit physical layout software program; (f) creating a physical design output data file according to said layed out physical circuit design structure wherein all circuit node locations are identified; (g) merging said created high voltage and physical design output data files; (h) creating a physical design input data file from said merging step, wherein, portions of said layed out physical circuit design structure, having nodes corresponding to a high voltage node, are identified; (i) inputting said physical design input data file to said computer system with said provided computer-aided circuit physical layout software program; (j) displaying on said graphical display device all circuit design structure corresponding to said physical design input data file, said display showing all suspect parasitic transistor regions in said circuit design structure, said displaying on said graphical display device all circuit design structure corresponding to said physical design input data file includes displaying pre-selected structures in a semiconductor epitaxial region capable of interacting with the structure to create said undesired parasitic transistors, said displaying pre-selected structures in a semiconductor epitaxial region includes identifying and displaying epitaxial regions in which a high voltage P-diffused region is not protected from low voltage regions such as low voltage P-diffused regions and low voltage overlying metallic region; and (k) identifying from said displaying step of said suspect parasitic transistor regions in said circuit design structure all undesirable parasitic transistors, said step of identifying includes highlighting, on said graphical display, epitaxial regions having an undesirable parasitic transistor configuration.

Claim 8

A high voltage nodal method for identifying undesirable parasitic transistors in an integrated circuit design layout during the computer-aided design of an integrated circuit, said computer-aided design including a computer system with peripheral devices for accepting and storing a circuit's design data and executing commercially available computer-aided circuit analysis and circuit physical layout software programs according to said circuit design data, said peripheral devices including a terminal graphical display device, said method comprising the steps of: (a) providing design data for a circuit being designed in an integrated circuit design manner, said step of providing design data includes providing input operating conditions, a reference high voltage value for comparison purposes and identification of the circuit nodes; (b) inputting said circuit design data into said computer system for storage into a designated design data file; (c) executing a circuit analysis run on said stored circuit design data using said provided computer-aided circuit analysis software program; (d) creating a high voltage output data file according to said executed circuit analysis run, wherein the only information contained is circuit nodal information concerning whether a node voltage value is greater than said reference high voltage value; (e) laying out a physical circuit design structure according to said stored circuit design data using said provided computer-aided circuit physical layout software program; (f) creating a physical design output data file according to said layed out physical circuit design structure wherein all circuit node locations are identified; (g) merging said created high voltage and physical design output data files; (h) creating a physical design input data file from said merging step, wherein, portions of said layed out physical circuit design structure, having nodes corresponding to a high voltage node, are identified; (i) inputting said physical design input data file to said computer system with said provided computer-aided circuit physical layout software program; (j) displaying on said graphical display device all circuit design structure corresponding to said physical design input data file, said display showing all suspect parasitic transistor regions in said circuit design structure, said displaying on said graphical display device all circuit design structure corresponding to said physical design input data file includes displaying pre-selected structures in a semiconductor epitaxial region capable of interacting with the structure to create said undesired parasitic transistors, said displaying pre-selected structures in a semiconductor epitaxial region includes identifying and displaying epitaxial regions in which a high voltage P-diffused region is not protected from low voltage regions such as low voltage P-diffused regions and low voltage overlying metallic region; and (k) identifying from said displaying step of said suspect parasitic transistor regions in said circuit design structure all undesirable parasitic transistors, said step of identifying includes highlighting, on said graphical display, epitaxial regions having an undesirable parasitic transistor configuration.