US5280195A
Expired / Lapsed
US
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Timing generator
Assignee: HEWLETT-PACKARD COMPANY A CA CORPORATION
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Filing: 1992-02-14
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Granted: 1994-01-18
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Expires: 2012-02-14
Abstract
Abstract A timing generator having no dead time and capable of altering a timing at any time. A rough timing pulse generating means suitably specifies one of a plurality of input clock pulses to generate a rough timing pulse for a desired timing. A timing vernier delays the rough timing pulse for a suitable delay time to generate a minute timing pulse. In a compensating circuit, the minute timing pulse is input to a delay circuit having one input terminal and plural output terminals, and one of the outputs at the output terminals for delay is selected by a multiplexer. When the multiplexer selects an output whose delay time is not zero, a next pulse can be input from the timing vernier to the dead time compensating circuit so that no dead time occurs.
Inventors
- 👤 Masaharu Goto
- 👤 Koh Murata
- 👤 Nobuyuki Kasuga
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 11:01
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/13; H03K5/131; H03K5/133
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
158 words
A timing generator for generating a desired timing signal in response to a master clock signal, comprising: means responsive to said master clock signal for generating a rough timing pulse as an approximation to said desired timing signal; first timing means responsive to said rough timing pulse for delaying said rough timing pulse so as to more closely approximate said desired timing signal; and second timing means independent of said first timing means which is responsive to said delayed rough timing pulse for further delaying said rough timing pulse so as to generate said desired timing signal, said second timing means comprising an input terminal, a plurality of output terminals, a plurality of delays and a selector, said input terminal being connected to said plurality of delays and output terminals so as to provide a plurality of delay paths, whereby said selector is operated to select a one of said delay paths which substantially eliminates a dead time.
Claim 2
Dependent Claim
158 words
A timing generator for generating a desired timing signal in response to a master clock signal, comprising: means responsive to said master clock signal for generating a rough timing pulse as an approximation to said desired timing signal; first timing means responsive to said rough timing pulse for delaying said rough timing pulse so as to more closely approximate said desired timing signal; and second timing means independent of said first timing means which is responsive to said delayed rough timing pulse for further delaying said rough timing pulse so as to generate said desired timing signal, said second timing means comprising an input terminal, a plurality of output terminals, a plurality of delays and a selector, said input terminal being connected to said plurality of delays and output terminals so as to provide a plurality of delay paths, whereby said selector is operated to select a one of said delay paths which substantially eliminates a dead time.
Claim 3
Dependent Claim
26 words
A timing generator according to claim 1 further comprising data latching means for independently controlling said first and second timing means in accordance with timing data.
Claim 4
Dependent Claim
36 words
A timing generator according to claim 2 wherein said data latching means controls said first timing means to generate a next desired timing signal while said second timing means is generating a current desired timing signal.
Claim 5
Dependent Claim
27 words
A timing generator according to claim 1 wherein one of said plurality of said delay paths has a substantially zero delay for substantially eliminating said dead time.
Claim 6
Dependent Claim
162 words
A timing generator for generating a desired timing signal in response to a master clock signal, comprising: first timing means responsive to said master clock signal for delaying said master clock signal so as to generate a delayed timing pulse as an approximation to said desired timing signal, said first timing means comprising an input terminal, a plurality of output terminals, a plurality of delays and a selector, said input terminal being connected to said plurality of delays and output terminals so as to provide a plurality of delay paths; means responsive to said delayed timing pulse for generating a rough timing pulse as a more close approximation to said desired timing signal; and second timing means responsive to said rough timing pulse for further delaying said rough timing pulse so as to generate said desired timing signal, whereby said selector selects one of said delay paths which generates a delayed timing pulse which causes a dead time to be substantially eliminated.
Claim 7
Dependent Claim
162 words
A timing generator for generating a desired timing signal in response to a master clock signal, comprising: first timing means responsive to said master clock signal for delaying said master clock signal so as to generate a delayed timing pulse as an approximation to said desired timing signal, said first timing means comprising an input terminal, a plurality of output terminals, a plurality of delays and a selector, said input terminal being connected to said plurality of delays and output terminals so as to provide a plurality of delay paths; means responsive to said delayed timing pulse for generating a rough timing pulse as a more close approximation to said desired timing signal; and second timing means responsive to said rough timing pulse for further delaying said rough timing pulse so as to generate said desired timing signal, whereby said selector selects one of said delay paths which generates a delayed timing pulse which causes a dead time to be substantially eliminated.
Claim 8
Dependent Claim
15 words
A timing generator according to claim 5 wherein said master clock is a non-periodic signal.
Claim 9
Dependent Claim
26 words
A timing generator according to claim 5 further comprising data latching means for independently controlling said first and second timing means in accordance with timing data.
Claim 10
Dependent Claim
36 words
A timing generator according to claim 7 wherein said data latching means controls said first timing means to generate a next desired timing signal while said second timing means is generating a current desired timing signal.
Claim 11
Dependent Claim
27 words
A timing generator according to claim 5 wherein one of said plurality of said delay paths has a substantially zero delay for substantially eliminating said dead time.
Claim 12
Dependent Claim
68 words
A timing generator according to claim 7 wherein said rough timing pulse generating means comprises a counter responsive to said master clock signal for generating a rough timing pulse and a one-shot gate responsive to said delayed timing signal, said rough timing pulse controlling loading of said one-shot gate to pass an output of said one-shot gate to said second timing means in accordance with said timing data.
Claim 13
Independent Claim
140 words
A method of substantially eliminating a dead time during the generation of a desired timing signal from a master clock signal, comprising the steps of: a) generating a rough timing pulse in response to said master clock signal as an approximation to said desired timing signal; b) delaying said rough timing pulse so as to more closely approximate said desired timing signals; c) delaying said delayed rough timing pulse so as to generate said desired timing signal, comprising the steps of: i) delaying said delayed rough timing pulse in different delay paths by different amounts of time, and ii) selecting an output of one of said delay paths which most closely approximates said desired timing signal; and d) controlling step b) independent of step c), whereby a combined delay in steps a)-c) causes said dead time to be substantially eliminated.
Claim 14
Independent Claim
140 words
A method of substantially eliminating a dead time during the generation of a desired timing signal from a master clock signal, comprising the steps of: a) generating a rough timing pulse in response to said master clock signal as an approximation to said desired timing signal; b) delaying said rough timing pulse so as to more closely approximate said desired timing signals; c) delaying said delayed rough timing pulse so as to generate said desired timing signal, comprising the steps of: i) delaying said delayed rough timing pulse in different delay paths by different amounts of time, and ii) selecting an output of one of said delay paths which most closely approximates said desired timing signal; and d) controlling step b) independent of step c), whereby a combined delay in steps a)-c) causes said dead time to be substantially eliminated.
Claim 15
Independent Claim
133 words
A method of substantially eliminating a dead time during the generation of a desired timing signal from a master clock signal, comprising the steps of: a) delaying said master clock signal in different delay paths by different amounts of time so as to generate a plurality of delayed timing pulses; b) selecting one of said plurality of delayed timing pulses as an approximation to said desired timing signal; c) generating a rough timing pulse in response to said one delayed timing pulse as a more close approximation to said desired timing signal; d) further delaying said rough timing pulse so as to generate said desired timing signal; and e) controlling steps a) and b) independent of step c), whereby a combined delay in steps a)-d) causes said dead time to be substantially eliminated.
Claim 16
Independent Claim
133 words
A method of substantially eliminating a dead time during the generation of a desired timing signal from a master clock signal, comprising the steps of: a) delaying said master clock signal in different delay paths by different amounts of time so as to generate a plurality of delayed timing pulses; b) selecting one of said plurality of delayed timing pulses as an approximation to said desired timing signal; c) generating a rough timing pulse in response to said one delayed timing pulse as a more close approximation to said desired timing signal; d) further delaying said rough timing pulse so as to generate said desired timing signal; and e) controlling steps a) and b) independent of step c), whereby a combined delay in steps a)-d) causes said dead time to be substantially eliminated.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-01-17 | 1997-07-19 | 1998-01-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-01-17 | 2001-07-19 | 2002-01-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-01-17 | 2005-07-19 | 2006-01-18 | $7700.00 | Window Closed / Lapsed |