← Back to Patent Explorer
US5279987A Expired / Lapsed US ⏱️ 0.0 years remaining

Fabricating planar complementary patterned subcollectors with silicon epitaxial layer

Assignee: International Business Machines Corp
•
Filing: 1991-10-31
•
Granted: 1994-01-18
•
Expires: 2011-10-31
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A process, compatible with bipolar and CMOS silicon device manufacturing for fabricating complementary buried doped regions in a silicon substrate. An N+ doped region (12) is formed in the silicon substrate by known methods of arsenic doping and drive in. This is followed by depositing a first thin epitaxial silicon cap layer (14), under conditions of minimum N+ autodoping. Part thickness of this first epilayer is converted to oxide (18), and the oxide is patterned to provide apertures in an area where it is desired to form a P+ region. A P source material (20) is deposited and a drive in anneal is used to dope the silicon with P in the areas of the oxide aperture opening. Subsequent to drive in, the dopant source layer and the oxide mask is removed by wet etching. An oxide is regrown on the surface, including the P+ region (22), and subsequently the oxide layer is stripped in dilute hydrofluoric acid. Next a second epitaxial silicon layer (28) is deposited to make up the total epi thickness to a desired value, using process conditions of minimum P doping.

Inventors

  • 👤 John S. Lechaton
  • 👤 Shaw-Ning Mei
  • 👤 Dominic J. Schepis
  • 👤 Mithkal M. Smadi

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 10:32
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0107; H10D84/0109; H10D84/02; H10D84/03; H10D84/038; H10P; H10P32/00; H10P32/10; H10P32/15; H10W; H10W15/00; H10W15/01; Y; Y10; Y10S; Y10S148/00; Y10S148/025

Claims Analysis

Total Claims: 9
Claim 1
Independent Claim 141 words
A method of manufacturing a substrate having complementary buried doped regions, comprising the steps: providing a semiconductor substrate having a top surface; doping said top surface to form a first buried region of N conductivity type; depositing a first layer of epitaxial intrinsic silicon over said top surface; oxidizing a partial thickness of said first layer of epitaxial intrinsic silicon to form a first layer of oxide; patterning said first oxide layer to provide an aperture; doping through said aperture to form a buried region of P type conductivity; stripping said first oxide layer used to form the aperture; oxidizing a partial thickness of said first layer of epitaxial region and said P doped region to form a second oxide layer; stripping said second oxide layer; and depositing a second layer of epitaxial silicon over said first layer of epitaxial silicon.
Claim 2
Independent Claim 141 words
A method of manufacturing a substrate having complementary buried doped regions, comprising the steps: providing a semiconductor substrate having a top surface; doping said top surface to form a first buried region of N conductivity type; depositing a first layer of epitaxial intrinsic silicon over said top surface; oxidizing a partial thickness of said first layer of epitaxial intrinsic silicon to form a first layer of oxide; patterning said first oxide layer to provide an aperture; doping through said aperture to form a buried region of P type conductivity; stripping said first oxide layer used to form the aperture; oxidizing a partial thickness of said first layer of epitaxial region and said P doped region to form a second oxide layer; stripping said second oxide layer; and depositing a second layer of epitaxial silicon over said first layer of epitaxial silicon.
Claim 3
Dependent Claim 36 words
The method as recited in claim 1, wherein the thickness of said first layer of epitaxy silicon is about 1500 to 3000 A thick, and the thickness of said first oxide layer is 500 to 1500A.
Claim 4
Dependent Claim 41 words
The method as recited in claim 1, wherein said buried region of P type conductivity is formed by the use of a solid dopant source, comprising borosilicate glass, 1000 to 2000 A in thickness, to thereby diffuse boron into said region.
Claim 5
Dependent Claim 55 words
The method as recited in claim 1, wherein said first layer epitaxial silicon is deposited by a two step process of 1) deposition of 1000 A at about 1050 to 1200 C and about 60 torr pressure, followed by the 2) deposition of the balance at about 900 C and at about 60 torr pressure.
Claim 6
Dependent Claim 27 words
The method as recited in claim 1, wherein said second layer of epitaxial silicon is deposited at about 900 C and at about 200 to 700 torr.
Claim 7
Dependent Claim 59 words
The method as recited in claim 1, wherein said second layer of epitaxial silicon is deposited by a two step process of 1 ) deposition of about 1000 A at about 850 C and at about 200 to 700 torr, followed by 2) deposition of the rest of the thickness at about 850 C and at about 100 torr.
Claim 8
Dependent Claim 30 words
The method as recited in claim 6, wherein the step two of the two step process, includes deposition of the expitaxial silicon at about 1100 C and about 100 torr.
Claim 9
Dependent Claim 30 words
The method as recited in claim 3, wherein said diffusion from said solid dopant source is performed at a temperature range of 900 to 1000 C for about 30 minutes.

References Cited (Backward Citations)

US3716422A Cited
US4579609A Cited
US4578128A Cited
US4696701A Cited
JPS63148620A Cited
US4830973A Cited
EP0320070A1 Cited
US4894349A Cited
US4859626A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1997-01-17 1997-07-19 1998-01-18 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2001-01-17 2001-07-19 2002-01-18 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2005-01-17 2005-07-19 2006-01-18 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag