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US5279983A
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Method of making a semiconductor memory device
Assignee: Samsung Electronics Co Ltd
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Filing: 1992-06-30
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Granted: 1994-01-18
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Expires: 2012-06-30
Abstract
Abstract A semiconductor memory device includes a cell array region and a peripheral circuit region, wherein a channel is formed to surround the cell array region, on a border region between the cell array region and peripheral circuit region. Also, a method for the semiconductor memory device is provided. Therefore, the conventional problem of degraded reliability of the conductive layer due to the step between the cell array region and peripheral circuit region, can be prevented. At the same time, the surface planarization of the peripheral circuit region can be attained.
Inventors
- 👤 Ji-hong Ahn
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 16:54
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10B12/30; H10B12/31; H10B12/318; H10W; H10W20/00; H10W20/01; H10W20/40
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
85 words
A method for manufacturing a semiconductor memory device having a cell array region, a peripheral circuit region, and a border region between said cell array region and peripheral circuit region, comprising the steps of: forming an insulating material layer on the whole surface of a semiconductor wafer; forming a ditch surrounding said cell array region in said insulating material layer on said border region; forming a channel composed of a first material inside said ditch; and removing said insulating material layer on said border region.
Claim 2
Independent Claim
85 words
A method for manufacturing a semiconductor memory device having a cell array region, a peripheral circuit region, and a border region between said cell array region and peripheral circuit region, comprising the steps of: forming an insulating material layer on the whole surface of a semiconductor wafer; forming a ditch surrounding said cell array region in said insulating material layer on said border region; forming a channel composed of a first material inside said ditch; and removing said insulating material layer on said border region.
Claim 3
Dependent Claim
21 words
A method for manufacturing a semiconductor memory device as claimed in claim 1, wherein said first material is a conductive material.
Claim 4
Dependent Claim
24 words
A method for manufacturing a semiconductor memory device as claimed in claim 1, wherein said first material is a polysilicon doped with an impurity.
Claim 5
Dependent Claim
100 words
A method for manufacturing a semiconductor memory device as claim in claim 1, wherein said step for forming said channel comprises the steps of: forming a first material layer by coating said first material on the whole surface of said insulating material layer having said ditch therein; filling the inside of said ditch in which said first material layer is already formed, with a second material; removing said first material layer except that inside said ditch by anisotropically etching said first material layer, using said second material as an etch-mask; and removing said second material and said insulating material layer.
Claim 6
Dependent Claim
20 words
A method for manufacturing a semiconductor memory device as claimed in claim 4, wherein said second material is a resist.
Claim 7
Dependent Claim
63 words
A method for manufacturing a semiconductor memory device as claimed in claim 5, wherein said step for filling said ditch is carried out such that said resist is coated on said first material layer thicker than the depth of said ditch, and then is etched-back until the top surface of that part of said first material layer besides inside said ditch is exposed.
Claim 8
Dependent Claim
58 words
A method for manufacturing a semiconductor memory device as claimed in claim 1, wherein said step for removing said insulating material layer is carried out such that, after forming said channel, a resist layer is formed on all portions excepting said border region, and then said insulating material layer is etched using said resist layer as an etch-mask.
Claim 9
Independent Claim
173 words
A method for manufacturing a semiconductor memory device having a cell array region, a peripheral circuit region, and a border region between said cell array region and peripheral circuit region, comprising the steps of: forming an insulating material layer on the whole surface of a semiconductor substrate; forming a recess on the source region of a transistor constituting each cell, which is positioned above and larger than said source region on said cell array region, and forming a ditch surrounding said cell array region on said border region, by partially removing said insulating material layer; forming a first material layer on the whole surface of the resultant structure, for forming a storage electrode; filling said recess and ditch with a second material on said first material layer; removing all of said first material layer except that inside said recess and ditch by anisotropically etching said first material layer, using said second material as an etch-mask; removing said second material; and removing said insulating material layer on said cell array region and border region.
Claim 10
Independent Claim
173 words
A method for manufacturing a semiconductor memory device having a cell array region, a peripheral circuit region, and a border region between said cell array region and peripheral circuit region, comprising the steps of: forming an insulating material layer on the whole surface of a semiconductor substrate; forming a recess on the source region of a transistor constituting each cell, which is positioned above and larger than said source region on said cell array region, and forming a ditch surrounding said cell array region on said border region, by partially removing said insulating material layer; forming a first material layer on the whole surface of the resultant structure, for forming a storage electrode; filling said recess and ditch with a second material on said first material layer; removing all of said first material layer except that inside said recess and ditch by anisotropically etching said first material layer, using said second material as an etch-mask; removing said second material; and removing said insulating material layer on said cell array region and border region.
Claim 11
Dependent Claim
25 words
A method for manufacturing a semiconductor memory device as claimed in claim 8, wherein said first material is a polycrystalline silicon doped with an impurity.
Claim 12
Dependent Claim
23 words
A method for manufacturing a semiconductor memory device as claimed in claim 8, wherein the number of said ditch is at least one.
Claim 13
Dependent Claim
109 words
A method for manufacturing a semiconductor memory device as claimed in claim 8, wherein said step for removing said insulating material layer on said cell array region and border region comprises the steps of: forming a third material layer on the whole surface of the obtained structure after removing said second material; forming a third material layer pattern by partially removing said third material layer to expose said cell array region and a portion of said border region; and removing said insulating material layer on said cell array region and border region, using said third material layer pattern as an etch-mask, and then removing said third material layer pattern.
Claim 14
Dependent Claim
41 words
A method for manufacturing a semiconductor memory device as claimed in claim 11, wherein said third material is a photosensitive material having an etch rate which is different from that of said insulating material layer with respect to a wet etching.
Claim 15
Dependent Claim
20 words
A method for manufacturing a semiconductor memory device as claimed in claim 12, wherein said third material is a photoresist.
Claim 16
Dependent Claim
43 words
A method for manufacturing a semiconductor memory device as claimed in claim 8, wherein a material which has an etch rate being different from that of said first material with respect to an anisotropic or isotropic etching is used as said second material.
Claim 17
Dependent Claim
20 words
A method for manufacturing a semiconductor memory device as claimed in claim 14, wherein said second material is a photoresist.
References Cited (Backward Citations)
US4882289A
Cited
US5171713A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-01-17 | 1997-07-19 | 1998-01-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-01-17 | 2001-07-19 | 2002-01-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-01-17 | 2005-07-19 | 2006-01-18 | $7700.00 | Window Closed / Lapsed |