Patent US5278801A successfully refreshed from Google Patents.
US5278801A
Expired / Lapsed
US
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Flexible addressing for drams
Assignee: HP Inc
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Filing: 1992-08-31
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Granted: 1994-01-11
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Expires: 2012-08-31
Abstract
Abstract A memory controller for controlling access to a memory includes a mapper for mapping a physical address to a row address and a column address that are suitable for addressing first and second memory devices having the same memory capacity but different addressing formats, a multiplexer for multiplexing the row address and the column address onto a set of address lines for addressing the memory and a circuit for generating control signals for controlling access to the memory. In a preferred embodiment, the first memory devices are 16 Mb DRAMs which require asymmetric addressing, and the second memory devices are 16 Mb DRAMs which require symmetric addressing. The memory controller of the invention generates a row address and a column address for addressing both types of memory devices without having knowledge of the types of memory devices that are present in the memory.
Inventors
- 👤 Scott A. Dresser
- 👤 Raymond A. Ward
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 21:41
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/18
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
98 words
A memory controller for controlling access to a memory, comprising: a means for mapping a physical address to a row address and a column address, that are suitable for addressing first memory devices having a first address format and second memory devices having a second address format, said first and second memory devices having the same memory capacity; means for multiplexing said row address and said column address onto a set of address lines for addressing the memory; and means for generating control signals for controlling access to the memory by said row address and said column address.
Claim 2
Dependent Claim
98 words
A memory controller for controlling access to a memory, comprising: a means for mapping a physical address to a row address and a column address, that are suitable for addressing first memory devices having a first address format and second memory devices having a second address format, said first and second memory devices having the same memory capacity; means for multiplexing said row address and said column address onto a set of address lines for addressing the memory; and means for generating control signals for controlling access to the memory by said row address and said column address.
Claim 3
Dependent Claim
32 words
A memory controller as defined in claim 1 wherein the first memory devices and the second memory devices require different numbers of column address bits and different numbers of row address bits.
Claim 4
Dependent Claim
67 words
A memory controller as defined in claim 1 wherein said means for mapping generates a row address and a column address that is suitable for addressing first memory devices comprising 16 Mb DRAMs which require a 12 bit row address and a 10 bit column address, and second memory devices comprising 16 Mb DRAMs which require an 11 bit row address and an 11 bit column address.
Claim 5
Dependent Claim
25 words
A memory controller as defined in claim 3, wherein said means for mapping generates a 12 bit row address and a 11 bit column address.
Claim 6
Dependent Claim
34 words
A memory controller as defined in claim 1 wherein said means for mapping includes means for mapping at least one bit of the physical address into both the row address and the column address.
Claim 7
Dependent Claim
26 words
A memory controller as defined in claim 2 wherein said means for mapping generates a row address and a column address having equal numbers of bits.
Claim 8
Dependent Claim
130 words
In a data processing system having a microprocessor that generates memory access requests which includes address bits of a memory block, a memory controller for responding to the memory access requests, and a memory, said memory comprising multiple memory chips of the same memory capacity, wherein at least one of said memory chips requires a symmetric addressing format and at least one of said chips requires an asymmetric addressing format, said memory controller comprising: a) an address mapper for mapping the address bits of each memory access request into a row address and a column address, wherein at least one of the address bits is mapped to both the row address and the column address; and b) means for forwarding the row address and the column address to the memory.
Claim 9
Dependent Claim
130 words
In a data processing system having a microprocessor that generates memory access requests which includes address bits of a memory block, a memory controller for responding to the memory access requests, and a memory, said memory comprising multiple memory chips of the same memory capacity, wherein at least one of said memory chips requires a symmetric addressing format and at least one of said chips requires an asymmetric addressing format, said memory controller comprising: a) an address mapper for mapping the address bits of each memory access request into a row address and a column address, wherein at least one of the address bits is mapped to both the row address and the column address; and b) means for forwarding the row address and the column address to the memory.
Claim 10
Dependent Claim
148 words
In a data processing system having a microprocessor that generates memory access requests which include address bits of a block of memory, a memory subsystem, comprising: a) a memory comprising memory chips of the same memory capacity, wherein at least one of said memory chips requires a symmetric address and at least one of said memory chips requires an asymmetric address; and b) a memory controller for responding to the memory access requests, comprising: i) an address mapper for mapping the address bits of each memory access request into a row address and a column address wherein at least one of the address bits is mapped to both the row address and the column address; and ii) means for forwarding the row address and the column address to the memory such that any extra bits in the column address or the row address are ignored by the memory.
Claim 11
Dependent Claim
148 words
In a data processing system having a microprocessor that generates memory access requests which include address bits of a block of memory, a memory subsystem, comprising: a) a memory comprising memory chips of the same memory capacity, wherein at least one of said memory chips requires a symmetric address and at least one of said memory chips requires an asymmetric address; and b) a memory controller for responding to the memory access requests, comprising: i) an address mapper for mapping the address bits of each memory access request into a row address and a column address wherein at least one of the address bits is mapped to both the row address and the column address; and ii) means for forwarding the row address and the column address to the memory such that any extra bits in the column address or the row address are ignored by the memory.
Claim 12
Dependent Claim
19 words
A memory subsystem as recited in claim 8 wherein the memory chips comprise dynamic random access memory (DRAM) chips.
Claim 13
Dependent Claim
16 words
Memory subsystem as recited in claim 9 wherein the memory chips comprise 16 megabit DRAM chips.
Claim 14
Dependent Claim
21 words
A memory subsystem as recited in claim 8 wherein the memory chips are organized into single in line memory modules (SIMMs).
Claim 15
Dependent Claim
17 words
A memory subsystem as recited in claim 11 wherein the memory chips comprise 16 megabit DRAM chips.
Claim 16
Dependent Claim
32 words
A memory subsystem as recited in claim 8 further comprising at least one additional memory chip of a memory capacity that differs from the memory capacity of other of the memory chips.
Claim 17
Dependent Claim
153 words
In a data processing system having a microprocessor, memory having at least one memory chip that employs symmetric addressing and at least one memory chip that employs asymmetric addressing, a memory controller and a microprocessor, a method comprising the steps of: a) receiving at the memory controller a memory block address from the microprocessor of a memory location to be accessed; b) mapping the memory block address from the microprocessor into a row address and a column address such that at least one bit in the memory block address is mapped to both the row address and the column address; c) forwarding said row address and said column address to the memory chips of the memory regardless of whether said memory chips employ symmetric addressing or asymmetric addressing; and d) ignoring at the memory chips, extra bits provided in the row address or the column address so that the memory block is accessed.
Claim 18
Dependent Claim
153 words
In a data processing system having a microprocessor, memory having at least one memory chip that employs symmetric addressing and at least one memory chip that employs asymmetric addressing, a memory controller and a microprocessor, a method comprising the steps of: a) receiving at the memory controller a memory block address from the microprocessor of a memory location to be accessed; b) mapping the memory block address from the microprocessor into a row address and a column address such that at least one bit in the memory block address is mapped to both the row address and the column address; c) forwarding said row address and said column address to the memory chips of the memory regardless of whether said memory chips employ symmetric addressing or asymmetric addressing; and d) ignoring at the memory chips, extra bits provided in the row address or the column address so that the memory block is accessed.
References Cited (Backward Citations)
US5204841A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-01-10 | 1997-07-12 | 1998-01-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-01-10 | 2001-07-12 | 2002-01-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-01-10 | 2005-07-12 | 2006-01-11 | $7700.00 | Window Closed / Lapsed |