Pin-hole patch method for implanted dielectric layer

Claim 1

A method of forming isolation for an integrated circuit comprising the steps of: (a) implanting oxygen and/or nitrogen into a silicon substrate at a desired first range of depths, D 1 , below a surface of the substrate, where a top portion of the substrate has or is to have a prespecified bulk conductivity of a first type; (b) annealing the substrate to thereby react the implanted oxygen and/or nitrogen with the silicon of the substrate and form a buried dielectric layer at the first range of depths, D 1 , where the formed dielectric layer is susceptible to having pin-hole defects and/or thin-sections; (c) implanting doping atoms into the silicon substrate at second range of depths, D 2 , below the surface of the substrate, where the doping atoms are selected to form a region having a conductivity opposite to the first conductivity type and where the second range of depths, D 2 , is substantially the same or within the first range of depths, D 1 , of the dielectric layer; and (d) again annealing the substrate to diffuse the implanted doping atoms and thereby from a reverse-biasable PN junction within or substantially near to existing, if any, pin-hole defects and/or thin-sections of the dielectric layer for the purpose of complementing or enhancing or reinforcing the isolation function of the dielectric layer or patching isolation weaknesses caused by said pin-hole and thin-section defects of the dielectric layer, if any.

Claim 2

A method of forming isolation for an integrated circuit comprising the steps of: (a) implanting oxygen and/or nitrogen into a silicon substrate at a desired first range of depths, D 1 , below a surface of the substrate, where a top portion of the substrate has or is to have a prespecified bulk conductivity of a first type; (b) annealing the substrate to thereby react the implanted oxygen and/or nitrogen with the silicon of the substrate and form a buried dielectric layer at the first range of depths, D 1 , where the formed dielectric layer is susceptible to having pin-hole defects and/or thin-sections; (c) implanting doping atoms into the silicon substrate at second range of depths, D 2 , below the surface of the substrate, where the doping atoms are selected to form a region having a conductivity opposite to the first conductivity type and where the second range of depths, D 2 , is substantially the same or within the first range of depths, D 1 , of the dielectric layer; and (d) again annealing the substrate to diffuse the implanted doping atoms and thereby from a reverse-biasable PN junction within or substantially near to existing, if any, pin-hole defects and/or thin-sections of the dielectric layer for the purpose of complementing or enhancing or reinforcing the isolation function of the dielectric layer or patching isolation weaknesses caused by said pin-hole and thin-section defects of the dielectric layer, if any.