Static random access memory including stress test circuitry

Claim 2

A static random access memory comprising: a memory cell array having a plurality of static memory cells arranged in a matrix manner, a plurality of word lines for selecting said memory cells, and a plurality of pairs of bit lines receiving and transmitting data between said memory cells; a word line driving circuit selecting a first predetermined number of word lines in accordance with an input address at the time of a normal operation, and simultaneously selecting all word lines or a second predetermined number of word lines, the second predetermined number of word lines being greater than the first predetermined number of word lines selected at the time of the normal operation, at the time of a voltage stress applying test operation; a column selection circuit connected to the pair of bit lines of each column, and selectively controlled by a column selection signal; a sense amplifying circuit connected to said column selection circuit; a writing circuit connected to said column selection circuit; and a bit line load circuit having two bit line load transistors each connected to the pair of bit lines of each column, for applying a predetermined bias voltage to said pair of bit lines at the time of the normal operation, and controlling the bias voltage not to be applied to at least one of said pair of bit lines at the time of the voltage stress test operation.

Claim 3

The static random access memory according to claim 1, wherein one of said two bit load transistors of said bit line load circuit is controlled to be in a high impedance state or in an off state.

Claim 4

The static random access memory according to claim 2, wherein said bit line load circuit has a first gate circuit for ANDing a first test signal for controlling a transition from the normal operation mode to the voltage stress test mode and a second test signal for determining which bit line load transistor should be controlled to be in a high impedance state, and a second gate for ANDing an inversion signal of said second test signal and said first test signal.

Claim 5

The static random access memory according to claim 1 or 2, wherein said two bit line load transistors of said bit line load circuit are respectively controlled to be in a high impedance state or in an off state at the time of the voltage stress test operation.

Claim 6

The static random access memory according to claim 4, further comprising a plurality of switching transistors connected between each bit line and a ground voltage wherein one of said switching transistors is connected to one bit line of a bit line pair and another of said switching transistors is connected to the other bit line of the bit line pair, wherein one of said switching transistors is controlled to be in an on state at the time of the voltage stress test operation.

Claim 7

The static random access memory according to claim 4, further comprising a plurality of switching transistors connected between each bit line and a ground voltage wherein both switching transistors, one is connected to one bit line side and the other is connected to the other bit line side, are controlled to be in an on state at the time of the voltage stress test, respectively.

Claim 8

The static random access memory according to claim 4, wherein said column selection circuit selects a third predetermined pair of the bit lines in accordance with an input address at the time of a normal writing operation, and simultaneously selects all bit lines or a fourth predetermined number of bit lines, the fourth predetermined number of bit lines being greater than the third predetermined number of bit lines selected at the time of the writing normal operation, at the time of the voltage stress test operation.

Claim 9

The static random access memory according to claim 1, wherein said memory cell array is divided into a plurality of blocks in a row direction, and has a main word line, which is formed in common to the plurality of blocks, and a sub-word line formed every block; and said word line driving circuit has a main world line driving circuit for driving said main word line, a block selection circuit for selecting the blocks of said memory cell array, and a sub-word line driving circuit for driving said sub-word line after obtaining AND of the output signals of said two circuits, wherein all sub-word lines or a second number of the sub-word lines, which is greater than a first number of sub-word lines selected at the time of the normal operation, are selected at the same time at the time of the voltage stress test operation.

Claim 10

The static random access memory according to claim 8, wherein said word lien driving circuit restricts at least the supply of the operation power of said sub-word line driving circuit at the time of the voltage stress test.

Claim 11

The static random access memory according to claim 1, wherein a control signal for a stress test is input from a dedicated pad or an external terminal.

Claim 12

The static random access memory according to claim 1, wherein a circuit for detecting the input of voltage, which is more than a power voltage, from the outside is provided, and the output of said circuit is used as a control signal for the stress test.

Claim 13

A static random access memory comprising: a memory cell array having a plurality of static memory cells arranged in a matrix manner, a plurality of word lines for selecting said memory cells, and a plurality of pairs of bit lines receiving and transmitting data between said memory cells; a word line driving circuit selecting a first predetermined number of word lines in accordance with an input address at the time of a normal operation, and simultaneously selecting all word lines or a second predetermined number of word lines, the second predetermined number of word lines being greater than the first predetermined number of word lines selected at the time of the normal operation, at the time of a voltage stress applying test operation; a column selection circuit connected to the pair of bit lines of each column, and selectively controlled by a column selection signal; a sense amplifying circuit connected to said column selection circuit; a writing circuit connected to said column selection circuit; and a bit line load circuit having two bit line load transistors each connected to the pair of bit lines of each column, for applying a first predetermined bias voltage to said pair of bit lines at the time of the normal operation, and for applying a second predetermined voltage, wherein the second predetermined voltage being less than the first predetermined voltage at the time of the normal operation, or for applying a ground voltage to said bit lines at the time of the voltage stress test operation.

Claim 14

A static random access memory comprising: a memory cell array having a plurality of static memory cells arranged in a matrix manner, a plurality of word lines for selecting said memory cells, and a plurality of pairs of bit lines receiving and transmitting data between said memory cells; a word line driving circuit selecting a first predetermined number of word lines in accordance with an input address at the time of a normal operation, and simultaneously selecting all word lines or a second predetermined number of word lines, the second predetermined number of word lines being greater than the first predetermined number of word lines selected at the time of the normal operation, at the time of a voltage stress applying test operation; a column selection circuit connected to the pair of bit lines of each column, and selectively controlled by a column selection signal; a sense amplifying circuit connected to said column selection circuit; a writing circuit connected to said column selection circuit; and a bit line load circuit having two bit line load transistors each connected to the pair of bit lines of each column, for applying a first predetermined bias voltage to said pair of bit lines at the time of the normal operation, and for applying a second predetermined voltage, wherein the second predetermined voltage being less than the first predetermined voltage at the time of the normal operation, or for applying a ground voltage to said bit lines at the time of the voltage stress test operation.

Claim 15

The static random access memory according to claim 12, further comprising a bias circuit for generating said second voltage; and a changing circuit for changing the connection of said pair of bit lines to an output node of said bias circuit or a ground node at the time of the voltage stress time, wherein said two bit load transistors are respectively controlled to be in a low impedance state at the time of the voltage stress time.

Claim 16

The static random access memory according to claim 12 or 13, wherein said column selection circuit selects a first predetermined number of pairs of the bit lines in accordance with an input address connected to said writing circuit at the time of a normal writing operation, and simultaneously selects all bit lines or a second predetermined number of pairs of bit lines, wherein the second predetermined number of pairs of bit lines is greater than the first predetermined number of pairs of bit lines selected at the time of the normal operation, at the time of a voltage stress test operation.