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US5276406A Expired / Lapsed US ⏱️ 0.0 years remaining

Low noise wide dynamic range amplifiers

Assignee: Trontech Inc
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Filing: 1992-02-13
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Granted: 1994-01-04
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Expires: 2012-02-13
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Abstract

Abstract Certain GaAs FET devices are employed to accomplish low noise performance and simultaneous high power handling capability, i.e. high dynamic range performance, in an amplifier using larger GaAs FET devices. Such devices are incorporated in different circuit configurations to achieve amplifiers having, simultaneously, a low noise figure, higher input/output intercept performance, higher output power, and improved ruggedness toward high input interfering signals, while not sacrificing other highly desirable terminal characteristics, (i.e. gain, VSWR, etc.).

Inventors

  • 👤 Stephen J. Samay
  • 👤 Charles S. Brand

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-08 01:22
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/189; H03F3/19; H03F3/193; H03F3/1935

Claims Analysis

Total Claims: 9
Claim 1
Independent Claim 184 words
An electronic amplifier having low noise performance and simultaneous high power handling capability comprising: an input terminal and an output terminal, input impedance matching means connected to said input terminal for matching the impedance at said terminal to said amplifier; a GaAs FET transistor device connected to said input impedance matching means for amplifying the signal at said input terminal, and output impedance matching means connected to said GaAs FET transistor device and to said output terminal for matching the impedance at said output terminal to said GaAs FET transistor device; said GaAs FET transistor device having the following characteristics: ______________________________________ Max. drain - source voltage (Vds) 12-17 V max. power dissipation (watts @25° C.) 4-8 W Saturated drain current (Idss) .25 minimum Max. gate-source voltage (Vgs) -5 V Transconductance (gm) 120-350 mS Pinch-off voltage -1 to -5 V ______________________________________ where the upper value of each of said characteristics having an upper value may vary by an amount between 0% and 50% of said upper value; and said input impedance matching means and said output impedance matching means each including an active circuit element.
Claim 2
Dependent Claim 184 words
An electronic amplifier having low noise performance and simultaneous high power handling capability comprising: an input terminal and an output terminal, input impedance matching means connected to said input terminal for matching the impedance at said terminal to said amplifier; a GaAs FET transistor device connected to said input impedance matching means for amplifying the signal at said input terminal, and output impedance matching means connected to said GaAs FET transistor device and to said output terminal for matching the impedance at said output terminal to said GaAs FET transistor device; said GaAs FET transistor device having the following characteristics: ______________________________________ Max. drain - source voltage (Vds) 12-17 V max. power dissipation (watts @25° C.) 4-8 W Saturated drain current (Idss) .25 minimum Max. gate-source voltage (Vgs) -5 V Transconductance (gm) 120-350 mS Pinch-off voltage -1 to -5 V ______________________________________ where the upper value of each of said characteristics having an upper value may vary by an amount between 0% and 50% of said upper value; and said input impedance matching means and said output impedance matching means each including an active circuit element.
Claim 3
Dependent Claim 30 words
The amplifier of claim 1 further including feedback network means connected across said GaAs FET transistor device for adjusting the gain and impedance level of said GaAs FET transistor device.
Claim 4
Dependent Claim 21 words
The amplifier of claim 1 wherein said input impedance matching means and said output impedance matching means includes passive circuit elements.
Claim 5
Dependent Claim 14 words
The amplifier of claim 2 wherein said feedback network means includes passive circuit elements.
Claim 6
Dependent Claim 14 words
The amplifier of claim 2 wherein said feedback network means includes active circuit elements.
Claim 7
Dependent Claim 200 words
An electronic amplifier circuit having low noise performance and simultaneous high power handling capability comprising: an input terminal and an output terminal, input signal splitting means connected to said input terminal for splitting said input signal into a plurality of signals; input impedance matching means connected to said input signal splitting means for each of said plurality of signals for matching the impedance at said input signal splitting means to a GaAs FET amplifier means; GaAs FET amplifier means connected to each of said input impedance matching means for amplifying the signal at said input impedance matching means, output impedance matching means connected to each of said GaAs FET amplifier means for matching the impedance at each of said GaAs FET amplifier means to an output signal combining means; output signal combining means connected to each of said output impedance matching means and to said output terminal for recombining said signal; said GaAs FET amplifier means having the following characteristics: ______________________________________ Max. drain - source voltage (Vds) 12-17 V max. power dissipation (watts @25° C.) 4-8 W Saturated drain current (Idss) .25 minimum Max. gate-source voltage (Vgs) -5 V Transconductance (gm) 120-350 mS Pinch-off voltage -1 to -5 V. ______________________________________
Claim 8
Dependent Claim 200 words
An electronic amplifier circuit having low noise performance and simultaneous high power handling capability comprising: an input terminal and an output terminal, input signal splitting means connected to said input terminal for splitting said input signal into a plurality of signals; input impedance matching means connected to said input signal splitting means for each of said plurality of signals for matching the impedance at said input signal splitting means to a GaAs FET amplifier means; GaAs FET amplifier means connected to each of said input impedance matching means for amplifying the signal at said input impedance matching means, output impedance matching means connected to each of said GaAs FET amplifier means for matching the impedance at each of said GaAs FET amplifier means to an output signal combining means; output signal combining means connected to each of said output impedance matching means and to said output terminal for recombining said signal; said GaAs FET amplifier means having the following characteristics: ______________________________________ Max. drain - source voltage (Vds) 12-17 V max. power dissipation (watts @25° C.) 4-8 W Saturated drain current (Idss) .25 minimum Max. gate-source voltage (Vgs) -5 V Transconductance (gm) 120-350 mS Pinch-off voltage -1 to -5 V. ______________________________________
Claim 9
Dependent Claim 21 words
The amplifier of claim 6 wherein said input signal splitting means and said output signal combining means include passive circuit elements.

References Cited (Backward Citations)

US4803443A Cited
US5015968A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1997-01-03 1997-07-05 1998-01-04 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2001-01-03 2001-07-05 2002-01-04 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2005-01-03 2005-07-05 2006-01-04 $7700.00 Window Closed / Lapsed

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