Clock speed limiter for a microprocessor by comparing clock signal with a predetermined frequency

Claim 2

In a microprocessor which operates under control of an input clocking signal and which is designated to operate when said input clocking signal is at a frequency which is within a first frequency range, a circuit for disabling the operation of said microprocessor when said frequency of said input clocking signal exceeds said first frequency range, said circuit comprising: a switched capacitor network having at least a first resistance which is a function of said frequency of said input clocking signal, said network being coupled to receive said input clocking signal; a resistor means for providing a second resistance, said resistor means being settable to one of a plurality of constant resistances, and is set to one of said plurality of constant resistances based on said first frequency range; comparator means having a first input coupled to said network and a second input coupled to said resistor means for comparing said first and second resistances, said comparator means responding to a change in said first resistance by providing a disable signal for disabling said microprocessor when said frequency of said input clocking signal exceeds said first frequency range.

Claim 3

The circuit defined by claim 1 wherein said resistor means is set using a programming means for providing said second resistance.

Claim 4

The circuit defined by claim 2 wherein said programming means provides a signal within said microprocessor for selecting an oscillator range.

Claim 5

The circuit defined by claim 2 wherein said programming means provides signals governing a phase gap in timing signals used in said microprocessor.

Claim 6

In a semiconductor device which operates under control of a clocking signal having a first frequency, and which is designated to operate when said first frequency is within a predetermined frequency range, an apparatus for providing a first signal when said first frequency of said clocking signal applied to said semiconductor device exceeds said predetermined frequency range comprising: comparator means having first and second inputs for providing said first signal when an input signal coupled to said first input of said comparator means exceeds a certain limit; said certain limit being a function of a first resistor means coupled to said second input of said comparator means wherein said input signal coupled to said first input of said comparator means is a function of a second resistor means; said first resistor means for providing a first resistance, wherein said first resistor means is settable to one of a plurality of constant resistances, and is set to one of said plurality of constant resistances based on said predetermined frequency range; said second resistor means comprising a switched capacitor network coupled to receive said clocking signal, while providing a second resistance which varies with said first frequency of said clocking signal.

Claim 7

In a semiconductor device which operates under control of a clocking signal having a first frequency, and which is designated to operate when said first frequency is within a predetermined frequency range, an apparatus for providing a first signal when said first frequency of said clocking signal applied to said semiconductor device exceeds said predetermined frequency range comprising: comparator means having first and second inputs for providing said first signal when an input signal coupled to said first input of said comparator means exceeds a certain limit; said certain limit being a function of a first resistor means coupled to said second input of said comparator means wherein said input signal coupled to said first input of said comparator means is a function of a second resistor means; said first resistor means for providing a first resistance, wherein said first resistor means is settable to one of a plurality of constant resistances, and is set to one of said plurality of constant resistances based on said predetermined frequency range; said second resistor means comprising a switched capacitor network coupled to receive said clocking signal, while providing a second resistance which varies with said first frequency of said clocking signal.

Claim 8

The apparatus defined by claim 5 wherein said first resistor means comprises at least one resistor formed in a well disposed in said semiconductor device and two spaced-apart regions of the same conductivity type as said well, said regions being separated from one another by a field oxide region.

Claim 9

The apparatus defined by claim 5 wherein said first resistor means is programmable such that said first resistance may have one of a plurality of predetermined values.

Claim 10

The apparatus defined by claim 7 wherein said first resistor means comprises bonding pads to which discretionary connections can be made.

Claim 11

The apparatus defined by claim 8 wherein said first resistor means includes a decoder coupled to said bonding pads, said decoder providing a signal within said device which prevents the output of said comparator means from disabling said device.