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US5274263A Expired / Lapsed US ⏱️ 0.0 years remaining

FET structure for use in narrow bandgap semiconductors

Assignee: Texas Instruments Inc
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Filing: 1991-01-28
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Granted: 1993-12-28
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Expires: 2011-01-28
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Abstract

Abstract A FET structure for use in narrow bandgap semiconductors comprising a narrow bandgap semiconductor substrate 24, an implanted source region 12 of a conductivity type opposite that of the substrate 24, an implanted drain region 12 of the same conductivity type as source region 12 and spaced from source region 12, a first diode guard ring 14 insulatively disposed on the substrate 24 and surrounding source region 12, a second diode guard ring 14 insulatively disposed on the substrate 24 and surrounding drain region 12, a gate region 16 insulatively disposed on the substrate 24 and surrounding the source and drain regions 12 and the first and second diode guard rings 14, an outer periphery transistor guard ring 18 insulatively disposed on the substrate 24 and surrounding the gate region 16 and a field plate region 20 insulatively disposed on the substrate 24 and surrounding the outer periphery transistor guard ring 18. Other devices, systems and methods are also disclosed.

Inventors

  • 👤 Mark V. Wadsworth

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-08 05:34
CPC Classifications
H; H10; H10D; H10D99/00; H10D30/00; H10D30/60; H10D62/00; H10D62/80; H10D62/86; H10D84/00; H10D84/01; H10D84/02; H10D84/07; H10F; H10F39/00; H10F39/10; H10F39/12; H10F39/15; H10F39/157

Claims Analysis

Total Claims: 26
Claim 1
Independent Claim 108 words
A FET structure for use in narrow bandgap semiconductors, comprising: a substrate of a first conductivity type having a first surface wherein said substrate is a narrow bandgap semiconductor; a source region of a second conductivity type at said first surface; a drain region of said second conductivity type at said first surface and spaced from said source region; a first diode guard ring insulatively disposed on said substrate wherein said first diode guard ring surrounds said source region; a second diode guard ring insulatively disposed on said substrate wherein said second diode guard ring surrounds said drain region; and a gate region insulatively disposed on said substrate.
Claim 2
Dependent Claim 108 words
A FET structure for use in narrow bandgap semiconductors, comprising: a substrate of a first conductivity type having a first surface wherein said substrate is a narrow bandgap semiconductor; a source region of a second conductivity type at said first surface; a drain region of said second conductivity type at said first surface and spaced from said source region; a first diode guard ring insulatively disposed on said substrate wherein said first diode guard ring surrounds said source region; a second diode guard ring insulatively disposed on said substrate wherein said second diode guard ring surrounds said drain region; and a gate region insulatively disposed on said substrate.
Claim 3
Dependent Claim 19 words
The FET structure of claim 1 wherein said gate region surrounds said first and said second diode guard rings.
Claim 4
Dependent Claim 38 words
The FET structure of claim 1 further comprising an outer periphery transistor guard ring insulatively disposed on said substrate wherein said outer periphery transistor guard ring surrounds said gate region and said first and second diode guard rings.
Claim 5
Dependent Claim 29 words
The FET structure of claim 3 further comprising a field plate region insulatively disposed on said substrate wherein said field plate region surrounds said outer periphery transistor guard ring.
Claim 6
Dependent Claim 13 words
The FET structure of claim 1 wherein said narrow bandgap semiconductor is HgCdTe.
Claim 7
Dependent Claim 179 words
A charge conversion amplifier circuit, comprising: an input terminal for application of a reference voltage; a capacitive sense node for converting charge to voltage; a reset FET for selectively applying said reference voltage to said sense node, said reset FET having a drain coupled to said input terminal and a source coupled to said sense node; and an amplifier coupled to said sense node for amplifying said voltage, said amplifier comprising at least one FET, said at least one FET comprising: a substrate of a first conductivity type having a first surface wherein said substrate is a narrow bandgap semiconductor; a source region of a second conductivity type at said first surface; a drain region of said second conductivity type at said first surface and spaced from said source region; a first diode guard ring insulatively disposed on said substrate wherein said first diode guard ring surrounds said source region; a second diode guard ring insulatively disposed on said substrate wherein said second diode guard ring surrounds said drain region; and a gate region insulatively disposed on said substrate.
Claim 8
Dependent Claim 179 words
A charge conversion amplifier circuit, comprising: an input terminal for application of a reference voltage; a capacitive sense node for converting charge to voltage; a reset FET for selectively applying said reference voltage to said sense node, said reset FET having a drain coupled to said input terminal and a source coupled to said sense node; and an amplifier coupled to said sense node for amplifying said voltage, said amplifier comprising at least one FET, said at least one FET comprising: a substrate of a first conductivity type having a first surface wherein said substrate is a narrow bandgap semiconductor; a source region of a second conductivity type at said first surface; a drain region of said second conductivity type at said first surface and spaced from said source region; a first diode guard ring insulatively disposed on said substrate wherein said first diode guard ring surrounds said source region; a second diode guard ring insulatively disposed on said substrate wherein said second diode guard ring surrounds said drain region; and a gate region insulatively disposed on said substrate.
Claim 9
Dependent Claim 19 words
The FET structure of claim 6 wherein said gate region surrounds said first and said second diode guard rings.
Claim 10
Dependent Claim 42 words
The charge conversion amplifier of claim 6 wherein said FET further comprises an outer periphery transistor guard ring insulatively disposed on said substrate wherein said outer periphery transistor guard ring surrounds said gate region and said first and second diode guard rings.
Claim 11
Dependent Claim 33 words
The charge conversion amplifier of claim 8 wherein said FET further comprises a field plate region insulatively disposed on said substrate wherein said field plate region surrounds said outer periphery transistor guard ring.
Claim 12
Dependent Claim 13 words
The FET structure of claim 1 wherein said narrow bandgap semiconductor is HgCdTe.
Claim 13
Dependent Claim 20 words
The charge conversion amplifier of claim 6 wherein said capacitive sense node is a floating diffusion disposed in said substrate.
Claim 14
Dependent Claim 196 words
A CCD imager having at least one charge conversion amplifier circuit formed on a substrate, each of said charge conversion amplifier circuits comprising: an input terminal for application of a reference voltage; a capacitive sense node for converting charge to voltage; a reset FET for selectively applying said reference voltage to said sense node, said reset FET having a drain coupled to said input terminal and a source coupled to said sense node; and an amplifier coupled to said sense node for amplifying said voltage, said amplifier comprising at least one FET, said at least one FET comprising: a substrate of a first conductivity type having a first surface wherein said substrate is a narrow bandgap semiconductor; a source region of a second conductivity type at said first surface; a drain region of said second conductivity type at said first surface and spaced from said source region; a first diode guard ring insulatively disposed on said substrate wherein said first diode guard ring surrounds said source region; a second diode guard ring insulatively disposed on said substrate wherein said second diode guard ring surrounds said drain region; and a gate region insulatively disposed on said substrate.
Claim 15
Dependent Claim 196 words
A CCD imager having at least one charge conversion amplifier circuit formed on a substrate, each of said charge conversion amplifier circuits comprising: an input terminal for application of a reference voltage; a capacitive sense node for converting charge to voltage; a reset FET for selectively applying said reference voltage to said sense node, said reset FET having a drain coupled to said input terminal and a source coupled to said sense node; and an amplifier coupled to said sense node for amplifying said voltage, said amplifier comprising at least one FET, said at least one FET comprising: a substrate of a first conductivity type having a first surface wherein said substrate is a narrow bandgap semiconductor; a source region of a second conductivity type at said first surface; a drain region of said second conductivity type at said first surface and spaced from said source region; a first diode guard ring insulatively disposed on said substrate wherein said first diode guard ring surrounds said source region; a second diode guard ring insulatively disposed on said substrate wherein said second diode guard ring surrounds said drain region; and a gate region insulatively disposed on said substrate.
Claim 16
Dependent Claim 19 words
The FET structure of claim 12 wherein said gate region surrounds said first and said second diode guard rings.
Claim 17
Dependent Claim 34 words
The charge conversion amplifier of claim 12 wherein said FET further comprises an outer periphery transistor guard ring insulatively disposed on said substrate wherein said outer periphery transistor guard ring surrounds said gate region.
Claim 18
Dependent Claim 33 words
The charge conversion amplifier of claim 14 wherein said FET further comprises a field plate region insulatively disposed on said substrate wherein said field plate region surrounds said outer periphery transistor guard ring.
Claim 19
Dependent Claim 13 words
The FET structure of claim 12 wherein said narrow bandgap semiconductor is HgCdTe.
Claim 20
Dependent Claim 20 words
The charge conversion amplifier of claim 12 wherein said capacitive sense node is a floating diffusion disposed in said substrate.
Claim 21
Independent Claim 121 words
A method of making a FET structure for use in narrow bandgap semiconductors, comprising the steps of: forming a substrate of a first conductivity type having a first surface wherein said substrate is a narrow bandgap semiconductor; implanting a source region of a second conductivity type at said first surface; implanting a drain region of said second conductivity type at said first surface and spaced from said source region; forming a first diode guard ring insulatively disposed on said substrate wherein said first diode guard ring surrounds said source region; forming a second diode guard ring insulatively disposed on said substrate wherein said second diode guard ring surrounds said drain region; and forming a gate region insulatively disposed on said substrate.
Claim 22
Independent Claim 121 words
A method of making a FET structure for use in narrow bandgap semiconductors, comprising the steps of: forming a substrate of a first conductivity type having a first surface wherein said substrate is a narrow bandgap semiconductor; implanting a source region of a second conductivity type at said first surface; implanting a drain region of said second conductivity type at said first surface and spaced from said source region; forming a first diode guard ring insulatively disposed on said substrate wherein said first diode guard ring surrounds said source region; forming a second diode guard ring insulatively disposed on said substrate wherein said second diode guard ring surrounds said drain region; and forming a gate region insulatively disposed on said substrate.
Claim 23
Dependent Claim 21 words
The method of claim 18, further comprising forming said gate region to surround said first and said second diode guard rings.
Claim 24
Dependent Claim 33 words
The method of claim 18, further comprising the step of forming an outer periphery transistor guard ring insulatively disposed on said substrate wherein said outer periphery transistor guard ring surrounds said gate region.
Claim 25
Dependent Claim 32 words
The method of claim 20, further comprising the steps of forming a field plate region insulatively disposed on said substrate wherein said field plate region surrounds said outer periphery transistor guard ring.
Claim 26
Dependent Claim 12 words
The method of claim 18 wherein said substrate is formed of HgCdTe.

References Cited (Backward Citations)

US4308549A Cited
US4751560A Cited
US4947222A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1996-12-27 1997-06-28 1997-12-28 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2000-12-27 2001-06-28 2001-12-28 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2004-12-27 2005-06-28 2005-12-28 $7700.00 Window Closed / Lapsed

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