Horizontal AFC (automatic frequency control) circuit

Claim 2

A horizontal AFC (automatic frequency control) circuit comprising: a first AFC circuit having a relatively long time constant, into which a horizontal synchronizing signal is supplied; a window generating circuit for generating an output having a predetermined width from an output of said first AFC circuit; a second AFC circuit having a relatively short time constant, into which the horizontal synchronizing signal is inputted, and for producing an output within a range of said predetermined width of the window generating circuit when said horizontal synchronizing signal is under a normal condition; an edge detecting circuit for producing edge outputs in accordance with edge portions of the output having a predetermined width from the window generating circuit; and a horizontal oscillation output circuit into which an output of the second AFC circuit and also an output of the edge detecting circuit, for outputting the output from the second AFC circuit as a horizontal oscillation output when said output from the second AFC circuit is present within the range of the predetermined width, and also for outputting the edge outputs when the output of the second AFC circuit is not present in the range of the predetermined width.

Claim 3

A horizontal AFC circuit as claimed in claim 1, wherein said edge detecting circuit synchronously differentiates said window output with a predetermined with from said window generating circuit, thereby producing said edge outputs corresponding to the edge portions of said window output.

Claim 4

A horizontal AFC circuit as claimed in claim 1, wherein said first AFC circuit is constructed of a PLL (phase-locked loop) circuit having a relatively long time constant, and said second AFC circuit is arranged by a PLL circuit having a relatively short time constant.

Claim 5

A horizontal AFC circuit as claimed in claim 1, wherein said horizontal oscillation output circuit is constructed of D-flip-flops, an AND gate circuit and an OR gate circuit.

Claim 6

A television receiver comprising at least: an A/D (analog-to-digital) converter for converting an analog picture signal into digital picture data; a memory unit for storing said digital picture data; a horizontal AFC circuit for automatically controlling a horizontal synchronizing signal contained in the analog picture signal to obtain a horizontal oscillation output and a clock signal; and a memory control unit for control reading/writing operations of said digital picture data into the memory unit in response to the horizontal oscillation output and the clock signal derived from the horizontal AFC circuit, said horizontal AFC circuit comprising: a first AFC circuit having a relatively long time constant, into which a horizontal synchronizing signal is supplied; a window generating circuit for generating an output having a predetermined width from an output of said first AFC circuit; a second AFC circuit having a relatively short time constant, into which the horizontal synchronizing signal is inputted, and for producing an output within a range of said predetermined width of the window generating circuit when said horizontal synchronizing signal is under a normal condition; an edge detecting circuit for producing edge outputs in accordance with edge portions of the output having a predetermined width from the window generating circuit; and a horizontal oscillation output circuit into which an output of the second AFC circuit and also an output of the edge detecting circuit, for outputting the output from the second AFC circuit as a horizontal oscillation output when said output from the second AFC circuit is present within the range of the predetermined width, and also for outputting the edge outputs when the output of the second AFC circuit is not present in the range of the predetermined width.

Claim 7

A television receiver comprising at least: an A/D (analog-to-digital) converter for converting an analog picture signal into digital picture data; a memory unit for storing said digital picture data; a horizontal AFC circuit for automatically controlling a horizontal synchronizing signal contained in the analog picture signal to obtain a horizontal oscillation output and a clock signal; and a memory control unit for control reading/writing operations of said digital picture data into the memory unit in response to the horizontal oscillation output and the clock signal derived from the horizontal AFC circuit, said horizontal AFC circuit comprising: a first AFC circuit having a relatively long time constant, into which a horizontal synchronizing signal is supplied; a window generating circuit for generating an output having a predetermined width from an output of said first AFC circuit; a second AFC circuit having a relatively short time constant, into which the horizontal synchronizing signal is inputted, and for producing an output within a range of said predetermined width of the window generating circuit when said horizontal synchronizing signal is under a normal condition; an edge detecting circuit for producing edge outputs in accordance with edge portions of the output having a predetermined width from the window generating circuit; and a horizontal oscillation output circuit into which an output of the second AFC circuit and also an output of the edge detecting circuit, for outputting the output from the second AFC circuit as a horizontal oscillation output when said output from the second AFC circuit is present within the range of the predetermined width, and also for outputting the edge outputs when the output of the second AFC circuit is not present in the range of the predetermined width.